3.3 V Connection to ADC_VREF When Replacing a MAX 10 SC Device with an SA Device
We are considering replacing a 10M08SCU169C8G with a 10M08SAU169C8G and would like to avoid a PCB revision if possible. On the existing PCB, pin D3 (VCCA3) of the SC device is connected to 3.3 V. When the SA device is installed, the same pin becomes ADC_VREF, so ADC_VREF would remain connected to 3.3 V. We do not intend to use the ADC or an external ADC reference. We understand that the MAX 10 Pin Connection Guidelines specify that ADC_VREF should be left unconnected (NC) when an external reference is not used. Under these conditions, would leaving ADC_VREF connected to 3.3 V affect device operation or reliability? Is a PCB revision to leave pin D3 unconnected required in order to use the SA device? Thank you for your guidance.Agilex 5 RCOMP_GTS connection change and its effect on HVIO input pins
Hi There, In the Pin Connection Guidelines below, the connection method for the RCOMP_GTS pins has been changed. https://docs.altera.com/r/docs/813266/current/pin-connection-guidelines/example-1-agilextm-5-devices-with-speed-and-power-grade-1v-2v-2e-and-3v Related KDB: Why do HVIO pins in an Agilex® 5 or Agilex® 3 FPGA HVIO bank appear to be non-functional after device configuration? | Altera Community - 353565 We have two questions. Is this change due to a change in the device itself (silicon or specification)? Or was only the document updated, with no change to the device? Why do the HVIO input pins stop working when RCOMP_GTS is floating? We thought the HVIO bank and the GTS transceiver bank were not related. Kindly advise. Thank you.
Introducing the Altera Community AI Responder — Beta
Altera is introducing the AI Responder, an assistant built into the Altera Community to help provide faster, context-aware guidance for Altera product questions. It uses relevant public Altera documentation and Knowledge Database content, with coverage continuing to expand. The AI Responder may provide source references and can hand off complex or out-of-scope questions to an Altera subject-matter expert. As a beta feature, responses may contain errors or omissions, so please review the sources and verify technical guidance against official Altera documentation before implementation. If the response does not fully address your question, add more context and tag ai_responder to continue the discussion. We welcome your feedback as we improve the Community experience.
Schematics/layout for TerasIC SoCKit rev. D with Cyclone V
Greetings! I am working with an ALTERA/TerasIC SoCKit development board for Cyclone V. I've downloaded the "SoCKit CD-ROM ( rev. D Hardware )" archive from www.terasic.com.tw, but it does not contain schematics or PCB layout files. What I want to do is access ~8 GPIO pins on the board, but it does not have a GPIO header. So I can either solder to the mysterious "AD-DA HDR" connector plus some LEDs/switches, or connect to one of the 3 groups of pins on the wide HSMC (one has 20 differential pairs, the other two have 60 pins each) using a Samtek connector. To do that, I need to know how the pins on the SoCKit's PCB connectors map to the 5CSXFC6D6F31C6 IC's pads. BTW, I really appreciate the board having pads for an Altera JTAG connector pads: EthernetBlaster can be used with it! --A.
Agilex 3 A3CZ100BM16AE7S – 3.3 V HVIO input always reads HIGH
Hi, I am bringing up a new board using an Agilex 3 A3CZ100BM16AE7S and I am seeing a strange issue with the HVIO input path. I am using Quartus Prime Pro 25.3.1. The FPGA configures successfully through JTAG, FPGA logic is running, HVIO outputs work correctly, and inputs on non-HVIO banks also work correctly. However, the 3.3 V HVIO inputs always appear to be read as logic HIGH. My current simple test uses: Device: A3CZ100BM16AE7S Quartus Prime Pro: 25.3.1 TP1: AF27 HVIO Bank: 5B Direction: Input I/O standard: 3.3-V LVCMOS VCCIO_HVIO = 3.3 V VCCPT_HVIO = 1.8 V VCC/VCCP = 0.75 V The FPGA power rails have been checked and appear correct. A very simple test was first used: TP1 is 3.3V HVIO pin and TP13 is non-HVIO pin TP13 <= TP1; When TP1 is physically LOW, TP13 still indicates that TP1 is HIGH. I also tested: TP13 <= not TP1; With TP1 physically at 0 V, TP13 becomes LOW, which again indicates that the FPGA internally sees TP1 as logic 1. I also tested the programmable weak pull-up/down on AF27 (HVIO pin). With weak pull-up enabled: TP1 ≈ 3.3 V (with the multi-meter) With weak pull-down enabled: TP1 ≈ 0 V (with the multi-meter) The weak pull-up/down therefore physically changes the voltage at the FPGA pin correctly. I then enabled the internal weak pull-up and added an external 1 kΩ resistor from TP1 to GND. The measured TP1 voltage becomes approximately: TP1 ≈ 150 mV which is consistent with the internal ~20 kΩ pull-up and external 1 kΩ pull-down. However, the FPGA still reads the input as HIGH. Has anyone seen a similar issue with Agilex 3 HVIO input buffers, particularly with the A3CZ100BM16A device ? Is there any additional HVIO input configuration, device setting, programming option, or known Quartus issue that I may be missing? As far as I understand, a standard 3.3-V LVCMOS input on an HVIO bank should work directly without requiring any special input-enable configuration. Any suggestions for further tests would be greatly appreciated. Thanks. PaulDECA MAX 10 ADC1/ADC2 via SMA – simultaneous or multiplexed?
Hello, According to the user manual, the MAX 10 device on DECA Arrow includes integrated dual ADCs, and each ADC supports one dedicated analog input DECA_User_manual.pdf. The SMA demo also shows that ANAIN1 and ANAIN2 are used as the first SMA input and second SMA input I would like to clarify the following: My application is dual-channel voltage/current measurement for impedance/RLC measurement up to about 100 kHz, so channel-to-channel phase accuracy is important. Thank you very much for any clarification.Updated .brd file for Stratix 10 GX dev kit
Referencing this post: EK-10M08E144 PCB .brd file corrupted | Altera Community - 302242 The .brd file that comes in the documentation at: https://www.altera.com/products/devkit/po-3028/stratix-10-gx-signal-integrity-development-kit-h-tile ...was done in Allegro, prior to version 16.6. The only available Allegro viewer gives an error because it was done prior to version 16.6, and you need the DB Doctor utility to update the file. The only way to get the DB Doctor utility is to install Allegro. If I had Allegro...I would not be installing the Allegro viewer. Altera: As mentioned in the post above (well over a year ago), it would make sense for you to update your files so customers can view the board of their $10K+ development board. How do we make that happen? Thanks!
Quartus Programmer 21.1: JTAG Server Error Code 82 – Port 1309 Cannot Be Bound
Hello Altera Community, I am working on an FPGA project using a Cyclone IV FPGA development board and an Altera USB-Blaster. I am currently unable to program the FPGA because Quartus Programmer cannot access the JTAG server. System details: - OS: Windows 11 64-bit - Software: Quartus Programmer 21.1 - Installation path: C:\intelFPGA\21.1\qprogrammer - Programmer: Altera USB-Blaster - FPGA: Cyclone IV development board The USB-Blaster is detected by Windows Device Manager and the driver is installed. The USB-Blaster also powers on normally. However, Quartus Programmer gives: "Attempted to access JTAG server -- internal error code 82 occurred" When I run: jtagconfig I get: Error when scanning hardware - Server error Sometimes it also hangs at: Connecting to server(s) [...] I checked the JTAG server using: jtagserver --status It reports: Installed JTAG server is 'C:\intelFPGA\21.1\qprogrammer\bin64\jtagserver.exe' Server is stopped Remote clients are disabled I tried reinstalling the JTAG server: jtagserver --install jtagserver --start But the server immediately stops. I also tried: net start "Altera JTAG Server" The result was: The Altera JTAG Server service could not be started. The service did not report an error. NET HELPMSG 3534. I then ran: jtagserver.exe --foreground and received: Unable to bind changedetect socket: 10048 Can't bind to TCP port 1309 - exiting I checked the port using: netstat -ano | findstr 1309 and found that TCP port 1309 was being used/listened to by another process, for example PID 12888. I tried terminating the process using: taskkill /F /PID 12888 but Windows reported: ERROR: The process with PID 12888 could not be terminated. Reason: There is no running instance of the task. I also tried stopping the JTAG server, reinstalling it, and restarting it. In addition, I already tried the following: 1. Disabled PCI Express → Link State Power Management. 2. Disabled USB Root Hub power saving ("Allow the computer to turn off this device to save power"). 3. Stopped the Print Spooler service. 4. Closed Quartus/Programmer-related applications. 5. Reinstalled the JTAG Server. 6. Restarted the computer. 7. Tried starting the JTAG server manually. 8. Checked TCP port 1309 using netstat. The problem still remains. My main questions are: 1. Why is Quartus Programmer 21.1 unable to start the JTAG Server? 2. What is causing TCP port 1309 to remain occupied? 3. Is there a known issue with Quartus Programmer 21.1 and Windows 11? 4. Is there a recommended patch, driver, or newer Quartus Programmer version for this problem? 5. Is it possible to configure the JTAG server to use another TCP port? 6. What is the correct way to completely remove and reinstall the JTAG Server on Windows 11? 7. Is there anything else I should check before reinstalling Quartus Programmer? I would appreciate any guidance on how to get the JTAG Server running so that jtagconfig can detect my USB-Blaster and FPGA. Thank you.
