Unable to unlock /intelFPGA_pro/17.1.1/hld/installed_packages
Description In version 17.1, installing the drivers for an OpenCL™ BSP can fail if the user does not have permisstion to write to the installation directory. (Due to a shared drive for example). The issue is that version 17.1 of the SDK for OpenCL now tries to write some files to the SDK installation directory during aocl install. Errors reported: touch: cannot touch '/intelFPGA_pro/17.1.1/hld/.inst_pkg_busy.marker': Permission denied Unable to unlock /intelFPGA_pro/17.1.1/hld/installed_packages Resolution In update 1, (version 17.1.1) the user can now set an environment variable to direct the installation script to save the files in a directory that the user has write permissions. >export AOCL_INSTALLED_PACKAGES_ROOT="/my_path/writeable_path/" >sudo aocl install or if the above commands do not work >sudo env AOCL_INSTALLED_PACKAGES_ROOT=/my_path/writeable_path/ aocl install Scheduled to be fixed in a future version of the SDK for OpenCL.Can I connect VCCIO of I/O bank 1 to 2.5 V for AS configuration with EPCQ or EPCQA device when using Cyclone® III, Cyclone® IV, or Intel® Cyclone® 10 LP device?
Description No, when you use EPCQ or EPCQA quad-serial configuration device for AS configuration, you cannot connect VCCIO of I/O bank 1 to 2.5 V in Cyclone® III, Cyclone® IV, or Intel® Cyclone® 10 LP device. This is because the minimum VOH of the FPGA is insufficient for driving EPCQ or EPCQA input pins. Resolution Use 3.0 V or 3.3 V for Bank 1 VCCIO in Cyclone III, Cyclone IV, and Intel Cyclone 10 LP devices when AS configuration with EPCQ or EPCQA devices is used.Is there any problem if a floating voltage exists on VCCIO and VCCPT before it is ramped up and after it is ramped down in Arria® 10 FPGA devices and Cyclone® 10 FPGA devices?
Description No, there is no problem if a floating voltage exists on VCCIO and VCCPT before it is ramped up and after it is ramped down in Arria® 10 FPGA devices and Cyclone® 10 FPGA devices. Leakage can occur between VCC and VCCIO as well as between VCC and VCCPT, which can cause both VCCIO and VCCPT to float up to a maximum approximation of 0.8V before the power supply is ramped up and after the power supply is ramped down. This is expected behavior, and if the power-up and power-down sequences are followed, it will neither cause any functional failure nor concern the device's reliability. This behavior can only be observed if the regulators were designed to leave the power supplies to float before they ramp up and after they ramp down. Resolution This is an expected behavior and will neither cause any functional failure nor reliability concern to the device if the power-up sequence and power-down sequence are followed. This behavior can only be observed if the regulators were designed to leave the power supplies to float before they ramp up and after they ramp down.Why the package plan of Intel® Cyclone® 10 LP devices found in Intel® Cyclone® 10 LP Core Fabric and General Purpose I/Os Handbook mismatch with Intel® Cyclone® 10 LP Pin-Out Files?
Description The package plan of Intel ®Cyclone® 10 LP devices is an initial release. Users should refer to the Pin-Out Files for Intel ®FPGA Devices webpage for the up-to-date version.Error: TBBmalloc: skip allocation functions replacement in ucrtbase.dll: unknown prologue for function _msize
Description Due to a problem in the Quartus® Prime Standard Edition Software version 24.1 or earlier, you may see this error message when generating Altera® IP on the Windows* 11 OS (Operating System). Resolution To work around this problem, follow these steps: Go to This PC, right-click, and select Properties. Click Advanced System Setting. In the Advanced tab, select Environment Variable. Under System variables, create a new variable with the name TBB_MALLOC_DISABLE_REPLACEMENT and value as 1. Click OK and restart the Quartus® Prime Software.Why does Questa* license fail to install in the Quartus® Prime Lite Edition Software version 24.1?
Description This problem is due to user setup changed to new NIC ID. The license does not match the current NIC ID. Resolution To workaround this problem, you need to regenerate the license using new NIC ID then update the environment variable method and restart the computer to get the license to operate properly.Why is the input register not registered in the negative input pins, rx_in[*](n) of the ALTLVDS_RX megafunction?
Description Due to a problem in the Quartus® Prime Standard Edition Software version 23.1 and earlier, you might see that the input register is not registered in the ALTLVDS_RX megafunction's negative input pins, rx_in[*](n). This is because the synthesis attributes "LVDS_RX_REGISTER=LOW" and "LVDS_RX_REGISTER=HIGH" are not assigned to the register in the Low-voltage differential signaling (LVDS) receiver interfaces. Resolution To work around the problem, add the following assignments in the Quartus® Settings File (.qsf): set_instance_assignment -name LVDS_RX_REGISTER LOW -to "altlvds_rx:ALTLVDS_RX_component|altlvdsrx_lvds_rx:auto_generated|altlvdsrx_lvds_ddio_in:ddio_in|ddio_l_reg" set_instance_assignment -name LVDS_RX_REGISTER HIGH -to "altlvds_rx:ALTLVDS_RX_component|altlvdsrx_lvds_rx:auto_generated|altlvdsrx_lvds_ddio_in:ddio_in|ddio_h_reg" This problem is currently scheduled to be fixed in a future release of the Quartus® Prime Standard Edition Software.Is there a known issue with simulating the Cyclone® 10 FPGA LP PLL IP using Verilog?
Description Due to a problem in the Quartus® Prime Standard Edition software version 17.0, the PLL simulation model is not instantiated for Cyclone® 10 FPGA LP devices when performing Verilog simulation. This issue does not apply when simulating the Cyclone® 10 FPGA LP PLL IP using VHDL. Resolution To fix this issue, install the patch below on top of Quartus® Prime Standard version 17.0 and follow the instructions to add extra steps in your simulation run script. if ![file isdirectory verilog_libs] { file mkdir verilog_libs } vlib verilog_libs/altera_mf_ver vmap altera_mf_ver ./verilog_libs/altera_mf_ver vlog -vlog01compat -work altera_mf_ver {c:/intelfpga/17.0/quartus/eda/sim_lib/altera_mf.v} quartus-17.0std-0.12std-windows.exe quartus-17.0std-0.12std-linux.run quartus-17.0std-0.12std-readme.txt This problem is fixed beginning with the Quartus® Prime Standard Edition software version 18.0.Why does the Clocked Video Input Intel® FPGA IP (CVI) and Clocked Video Output Intel® FPGA IP (CVO) not available in the IP Catalog of Platform Designer?
Description The Clocked Video Input Intel® FPGA IP (CVI) and Clocked Video Output Intel® FPGA IP (CVO) are End Of Life (EOL) and no longer supported starting with the Intel® Quartus® Prime Standard Edition Software version 19.1 and later. Resolution Starting with the Video and Image Processing Suite User Guide version 19.4 and later, the information about Clocked Video Input Intel® FPGA IP and Clocked Video Output Intel® FPGA IP has been removed.What Power Delivery Network (PDN) Tool is available for the Intel® Cyclone® 10 devices?
Description For the Intel® Cyclone® 10 LP devices you may use the Device Agnostic Power Delivery Network (PDN) Tool. Look for the download link with '(device agnostic)' at its right. For the Intel® Cyclone® 10 GX devices, use the 'Power Delivery Network (PDN) Tool for Intel Stratix® 10, Intel Arria® 10 and Intel Cyclone® 10 GX Devices' You may obtain a copy of either PDN from Power Distribution Network Design Tool.