Cyclone V HPS FPGA2SDRAM Clock Queries
Dear Intel and all, Having some very puzzling behavior on HPS SDRAM and FPGA fabric bridge. If a fast clock i.e. 148MHz is running on 128bit AXI3 aka f2h_sdram0 mostly read action. And another AXI3 is using the remain 128bit bus with 144MHz aka f2h_sdram1 mostly on write. As such the system will stuck on distro aka Linux. With all these background could engineer or internal stuffs help. What is the restriction or constraints to use these bus under safe and stable speed? Forgot to provide stable situation: If the write dominated bus is reduced to 100MHz then the system is stable and no stall is found. So this makes a very strong feeling that the write cache is having issue? maybe CMA insufficient? Brian
MSGDMA ST-to-MM: Linux Driver Necessity & F2SDRAM Path Feasibility
Hello everyone, I am currently working on an MSGDMA implementation. I have verified that I can read the MSGDMA CSR and Descriptor registers via the LWH2F bridge using devmem2. My setup is configured in Streaming-to-Memory-Mapped (ST-to-MM) mode. I have two specific questions regarding this setup: 1、Is configuring the MSGDMA Linux kernel driver a mandatory condition for the hardware to function correctly? Is it possible to bypass the driver and configure the MSGDMA to start data transfer directly using devmem2 (user-space access)? 2、I noticed that some implementations write to the PS-side memory via the FPGA-to-HPS bridge. However, my design utilizes the F2SDRAM link, as indicated by the numbered sequence in the attached diagram. Could you please confirm if this architectural approach is feasible?
Agilex 5 with HPS Cryptographic services and bootflow
Hi I have a question regarding boot flow on agilex 5 with HPS with security in mind. I am aware how this is typically implemented on other SoCs like NXP but as for the Agilex - I just started working on this SoC From what I understand (based on the docs and tf-a source code in particular VAB part) the flow is the following: SDM verfies fsbl signature and loads it SDM releses HPS from reset Fsbl loads next stages (BL31 BL33) each time communicating with SDM through mailbox asking SDM to verify the image signaturure Then we can be sure that we only use legitimate binaries. Am I right? I have found in the agilex 5 product table that some variants are equipped with Cryptographic services and some not. Are these Cryptographic services needed to perform the above flow? If the variant I have is not equipped with such IP is there any other way to securely boot all boot chain up to Linux?
Arria 10 SoC Dev Kit Baremetal HPS examples issue & workflow
Hi, I recently acquired an Arria 10 SoC dev kit but I'm really struggling to run either the examples on embedded-software/bare-metal or the ones included in SoC EDS pro 20.1, trying to follow the instructions for both of them, they seem to rely on a old version of SoC EDS which included within ARM DS-5 and the toolchain, but now SoC EDS & ARM DS are separated and I cannot build the examples. With the new applications the flow for using this examples should remain the same? I mean: use Pogrammer to program the included .sof inside ghrd (or generate a updated one) -> open ARM-DS from SoC-EDS with environmental variables assigned and build with new toolchain arm-none-eabi -> run from ARM-DS (can i without license?) Seems like most of the tools used for running this examples have been discontinued (for example ) so at this point I don't know which workflow should I actually follow. PD: finally I was able to generate de application.axf from this example Altera-SoCFPGA-HardwareLib-16550-CV-GNU with an old toolchain but I don't know how to program it without a license, for now I don't want to debug anything, just do some simple tests printing by uartAgilex 5 HPS TEE
Hi, Is Arm Trust Zone supported on HPS? If so is the implementation of TEE supported on Agilex 5? I've checked TF-A sources and it seems that BL2 on this platform loads only BL31 and BL33. How about BL32? Is there an OP-TEE support? If not, are there any plans to provide it in the nearest feature?
Routing PL DDR to PS
We have an Arria 10 board with bad traces between the DDR memory and the hard memory controller for the PS. The PL has additional DDR memory not connected to the PS that works fine. Does a workaround exist that allows us to route the DDR memory connected to the PL and use it for Linux on the PS?
SDRAM calibration failed.
Hello, after Enpirion stopped selling some of the parts we used on our board, we had to redesign it. We assembled ten boards, and on two of them, I’m now getting an SDRAM calibration error in U-Boot. I’d like to enable the SDRAM calibration report to understand the cause of the error. However, the described method of adding. #define RUNTIME_CAL_REPORT 1 in the sequencer_defines.h file didn’t work. I generated the files using the QTS filter script, but there was no change. Could you please tell me how to properly enable the SDRAM calibration report so I can debug the issue?
