Stratix 10 Linux SD card booting
Hi Altera Community, I tried multiple attempts to boot the SD card from Rocketboard.org. https://releases.rocketboards.org/ I downloaded and booted the SD card with the .wic image file. It only has the .itb file by default in the boot partition. Whenever I try to boot, it asks for the U-Boot.img file. And also it says "failed to load "socfpga_stratix10_socdk.dtb" even if the file is there. And then I compiled my simple HPS design and can easily program the FPGA from the Quartus Programmer (rbf and sof file), but whenever I try to overlay it, like say: echo overlay.dtb > /sys/kernel?config?device-tree/overlays/0/path It says "FPGA manager error, timeout," and so on. Does any community member have notes or steps that you made to boot the SD card of the Stratix 10 FPGA? I am following this link: https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderStratix10
F2SDRAM fails to synthesize with custom logic
Hello guys, We are using Agilex5 SOC F2SDRAM bridge. I am trying to connect custom logic to the F2SDRAM, but it absolutely refuses to synthesize unless I export the signals directly to the top-level ports. Does anyone know why this is happening? Also, is there an example design for F2SDRAM available? The GHRD is not very helpful since it only includes the JTAG master. I suspect it might be a design issue, so I even removed the adapter and connected it only within Qsys, but it’s still acting up like this. Does anyone know why this is happening even though everything is clearly declared and connected? HudsonAgilex 5/3 FreeRTOS Heterogeneous SMP SDK Release
Stable Version: v26.1 Quartus Version: 26.1 Supported devices: Agilex™ 3 and Agilex™ 5 Source: https://github.com/Ignitarium-Technology/freertos-socfpga Branch/Tag: v26.1-HSMP Release Date: June 24, 2026 Hello Everyone, A new version of the FreeRTOS SDK for Agilex 5/3 is now available. Apart from other fixes and features, the FreeRTOS port now supports heterogeneous SMP for Agilex™ 5 devices. Visit the GitHub repository for instructions on how to get started. Features and Comments Feature Agilex3 Agilex5 Agilex3 SMP Agilex5 SMP Supported Features Limitations / Known Issues A55 boot Yes Yes Yes Yes Single-core boot, Dual-core SMP, Quad-core SMP (Agilex 5) A76 boot NA Yes NA Yes Single-core boot, Dual-core SMP, Quad-core SMP QSPI boot Yes Yes Yes Yes eMMC boot Yes Yes Yes Yes SD boot Yes Yes Yes Yes NAND boot No No No No Clock Manager Yes Yes Yes Yes API to get clock speed of different blocks Reset Manager Yes Yes Yes Yes Peripheral reset assert/de-assert DMA driver Yes Yes Yes Yes Memory-to-Memory, Memory-to-Peripheral and Peripheral-to-Memory GPIO driver Yes Yes Yes Yes Write, read and interrupt support Timer driver Yes Yes Yes Yes User-defined and free-running modes UART driver Yes Yes Yes Yes Full-duplex TX and RX DMA not supported (planned for future release) I2C driver Yes Yes Yes Yes Master/Slave mode, standard and fast modes QSPI driver Yes Yes Yes Yes QSPI flash read/write/erase I3C driver Yes Yes Yes Yes Master mode, I3C and legacy I2C devices IBI not supported (planned for future release) SPI driver Yes Yes Yes Yes Master/Slave mode write and read NAND driver No No No No SDM Mailbox driver Yes Yes Yes Yes SDM commands with SIP_SVC SMMU support Yes Yes Yes Yes Static identity mapping for cache coherency SDMMC driver Yes Yes Yes Yes Standard and HS speeds, SDMMC and eMMC devices, FATFS support Ethernet stack Yes Yes Yes Yes TCP/IP, UDP, ICMP, DHCP, IPv4 and IPv6 USB 2.0 stack NT Yes NT Yes USB mass storage class Tested with a custom board and SOF USB 3.1 stack NT Yes NT Yes USB mass storage operation WDT driver Yes Yes Yes Yes Interrupt or reset on timer expiry EDAC support Yes Yes Yes Yes Error injection and detection for EMAC, USB and QSPI blocks OCRAM not supported IOSSM driver Yes Yes Yes Yes Error injection and detection Bridge driver Yes Yes Yes Yes Enable/Disable bridges Reboot Manager Yes Yes Yes Yes Warm/Cold reboot FPGA Manager Yes Yes Yes Yes FPGA configuration Legend: Yes: Feature available and tested No: Feature not available in SDK NA: Not applicable NT: Not tested Note: If you find any issues, please raise an issue on the GitHub repository. For more support and assistance, visit our website.
Unstable fpga programming using HPS(Agilex3)
Hi I have a problem where the fpga programming sometime fail when using the overlay method described here under "Reconfiguring Core Fabric from Linux": https://altera-fpga.github.io/rel-25.3.1/embedded-designs/agilex-3/c-series/boot-examples/ug-linux-boot-agx3/#reconfiguring-core-fabric-from-u-boot Here I have first two successful attempt then it fail on the third: root@agilex3:~# rmdir /sys/kernel/config/device-tree/overlays/0 ; sleep 1 ; mkdir /sys/kernel/config/device-tree/overlays/0 ; cd /lib/firmware/ ; sleep 1; echo overlay.dtb >/sys/kernel/config/device-tree/overlays/0/path rmdir: '/sys/kernel/config/device-tree/overlays/0': No such file or directory [ 182.671913] fpga_manager fpga0: writing overlay.rbf to Stratix10 SOC FPGA Manager [ 184.865664] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-region/firmware-name [ 184.876007] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-region/config-complete-timeout-us root@agilex3:/lib/firmware# rmdir /sys/kernel/config/device-tree/overlays/0 ; sleep 1 ; mkdir /sys/kernel/config/device-tree/overlays/0 ; cd /lib/firmware/ ; sleep 1; echo overlay.dtb >/sys/kernel/config/device-tree/overlays/0/path [ 196.530735] fpga_manager fpga0: writing overlay.rbf to Stratix10 SOC FPGA Manager [ 198.659279] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-region/firmware-name [ 198.669650] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-region/config-complete-timeout-us root@agilex3:/lib/firmware# rmdir /sys/kernel/config/device-tree/overlays/0 ; sleep 1 ; mkdir /sys/kernel/config/device-tree/overlays/0 ; cd /lib/firmware/ ; sleep 1; echo overlay.dtb >/sys/kernel/config/device-tree/overlays/0/path [ 214.383163] fpga_manager fpga0: writing overlay.rbf to Stratix10 SOC FPGA Manager [ 217.508857] arm-smmu-v3 16000000.iommu: CMD_SYNC timeout at 0x00004405 [hwprod 0x00004408, hwcons 0x00004405] [ 217.509907] arm-smmu-v3 16000000.iommu: CMD_SYNC timeout at 0x00004407 [hwprod 0x00004408, hwcons 0x00004405] U-Boot SPL 2025.10 (May 18 2026 - 08:34:29 +0000) Reset state: Cold MPU 800000 kHz L4 Main 400000 kHz L4 sys free 100000 kHz L4 MP 200000 kHz L4 SP 100000 kHz SDMMC 200000 kHz init_mem_cal: Initial DDR calibration IO96B_0 succeed DDR: Calibration success is_mailbox_spec_compatible: IOSSM mailbox version: 1 LPDDR4: 1792 MiB ecc_interrupt_status: ECC error number detected on IO96B_0: 0 SDRAM-ECC: Initialized success Does anybody know how to debug and fix this? I'm using Quartus Prime Version 25.3.0 Build 109 Devboard: DK-A3W135BM16AEA: Agilex™ 3 FPGA and SoC C-Series Development Kit
U-Boot "Synchronous Abort" boot failure on Terasic Atum A5 Rev B via Quartus 24.3 .jic generation
I am reaching out for technical assistance regarding a reproducible boot failure on the Terasic Atum A5 Rev B development board (Agilex 5) when using Quartus Prime Pro 24.3. I am attempting to compile a custom design that utilizes the Lightweight HPS-to-FPGA (lwhps2fpga) bus. My current workflow is as follows: Compile the project in Quartus 24.3 to generate the .sof file. Merge the .sof with the official Terasic FSBL .hex file. Use the Programming File Generator (PFG) to create a .jic file. Flash the .jic to the QSPI. The Issue: When flashing the .jic generated by this workflow, the boot process fails during the main U-Boot phase. The U-Boot SPL and ATF (BL31) load successfully. However, after U-Boot attempts to load the environment, the system crashes with a "Synchronous Abort" handler (esr 0x96000010, far 0x108d2000). This triggers a CPU reset with the message ### ERROR ### Please RESET the board ###. (I have attached the full UART terminal log of the boot sequence for reference). Isolation Testing: To isolate the issue from my custom logic, I applied this exact same compilation and .jic generation workflow to the official Terasic GHRD bundled with the board. The result was identical—the GHRD .jic generated by Quartus 24.3 crashes at the exact same U-Boot Synchronous Abort. Conversely, when I bypass compilation and simply flash the original, pre-compiled .jic provided in the Terasic resource package, the board boots into Linux flawlessly. This confirms the physical hardware is fully functional and the issue is strictly isolated to the .jic files being generated by the 24.3 workflow. Questions: Is there a known issue or missing step in the Quartus 24.3 workflow when merging the FSBL or configuring the .jic for the Agilex 5 that would cause U-Boot to encounter a Data Abort (likely when probing the AXI bridges)? What are the exact PFG parameters or required patches to successfully generate a booting .jic for this board under the 24.3 release? I look forward to your guidance on resolving this workflow issue
Agilex7m i have configure 4GB ddr linux is not booting. I got architect time failure error.
Agilex7m I have configure 2GB DDR, linux is booting fine. But if I configure 4GB ddr linux is not booting. I got architect time failure error. But 2GB ddr configuration this error not came. I u-boot 4GB ddr is accessible but linux is not booting Boot logs init_mem_cal: Initial DDR calibration IO96B_0 succeed DDR: Calibration success is_mailbox_spec_compatible: IOSSM mailbox version: 1 DDR5: 4096 MiB ecc_interrupt_status: ECC error number detected on IO96B_0: 0 DDR5: size check success DDR5: firewall init success DDR5 init success QSPI: Reference clock at 500000 kHz Trying to boot from SPI Board ID is not in range 0 to 255 ## Checking hash(es) for config board-0 ... OK ## Checking hash(es) for Image atf ... crc32+ OK ## Checking hash(es) for Image uboot ... crc32+ OK ## Checking hash(es) for Image fdt-0 ... crc32+ OK NOTICE: BL31: v2.13.1(release):QPDS25.3.1_REL_GSRD_PR NOTICE: BL31: Built : 10:40:22, Nov 25 2025 U-Boot 2025.10-ga0db71cfad37-dirty (Dec 11 2025 - 10:49:42 +0000)socfpga_agilex7m CPU: Altera FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53) Model: SoCFPGA Agilex7-M SoCDK DRAM: 2 GiB (total 4 GiB) Core: 38 devices, 22 uclasses, devicetree: separate NAND: 0 MiB MMC: mmc@ff808000: 0 Loading Environment from FAT... OK In: serial@ffc02000 Out: serial@ffc02000 Err: serial@ffc02000 Board ID is not in range 0 to 255 Net: eth0: ethernet@ff800000 Hit any key to stop autoboot: 0 SOCFPGA_AGILEX7M # SOCFPGA_AGILEX7M # SOCFPGA_AGILEX7M # SOCFPGA_AGILEX7M # bdinfo boot_params = 0x0000000000000100 DRAM bank = 0x0000000000000000 -> start = 0x0000000000000000 -> size = 0x0000000080000000 DRAM bank = 0x0000000000000001 -> start = 0x0000000100000000 -> size = 0x0000000080000000 flashstart = 0x0000000000000000 flashsize = 0x0000000000000000 flashoffset = 0x0000000000000000 baudrate = 115200 bps00 8N1 | NOR | Minicom 2.9 | VT102 | Offline | ttyACM0 relocaddr = 0x000000007fee9000 reloc off = 0x000000007fce9000 Build = 64-bit current eth = ethernet@ff800000 ethaddr = b6:97:a4:21:e2:4a IP addr = 169.254.65.121 fdt_blob = 0x000000007fae1950 lmb_dump_all: memory.count = 0x2 memory[0] [0x0-0x7fffffff], 0x80000000 bytes, flags: none memory[1] [0x100000000-0x17fffffff], 0x80000000 bytes, flags: none reserved.count = 0x3 reserved[0] [0x0-0x1ffffff], 0x2000000 bytes, flags: no-map reserved[1] [0x7eae1940-0x7fffffff], 0x151e6c0 bytes, flags: no-overwrite reserved[2] [0x17fff7000-0x17fffffff], 0x9000 bytes, flags: no-notify, no-overwrite devicetree = separate serial addr = 0x00000000ffc02000 width = 0x0000000000000004 shift = 0x0000000000000002 offset = 0x0000000000000000 clock = 0x0000000005f5e100 arch_number = 0x0000000000000000 TLB addr = 0x000000007ffe0000 irq_sp = 0x000000007fae1940 sp start = 0x000000007fae1940 Early malloc usage: 1608 / 2000 Failure log: init_mem_cal: Initial DDR calibration IO96B_0 succeed DDR: Calibration success is_mailbox_spec_compatible: IOSSM mailbox version: 1 DDR5: 4096 MiB ecc_interrupt_status: ECC error number detected on IO96B_0: 0 DDR5: size check success DDR5: firewall init success DDR5 init success QSPI: Reference clock at 500000 kHz Trying to boot from SPI Error: -22 Trying to boot from MMC1 Board ID is not in range 0 to 255 ## Checking hash(es) for config board-0 ... OK ## Checking hash(es) for Image atf ... crc32+ OK ## Checking hash(es) for Image uboot ... crc32+ OK ## Checking hash(es) for Image fdt-0 ... crc32+ OK NOTICE: BL31: v2.13.1(release):QPDS25.3.1_REL_GSRD_PR NOTICE: BL31: Built : 10:40:22, Nov 25 2025 U-Boot 2025.10 (Dec 11 2025 - 10:49:42 +0000)socfpga_agilex7m CPU: Altera FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53) Model: SoCFPGA Agilex7-M SoCDK DRAM: 2 GiB (total 4 GiB) Core: 38 devices, 22 uclasses, devicetree: separate NAND: 0 MiB MMC: mmc@ff808000: 0 Loading Environment from FAT... OK In: serial@ffc02000 Out: serial@ffc02000 Err: serial@ffc02000 Board ID is not in range 0 to 255 Net: eth0: ethernet@ff800000 Hit any key to stop autoboot: 0 switch to partitions #0, OK mmc0(part 0) is current device Scanning mmc 0:1... Found U-Boot script /boot.scr.uimg 2411 bytes read in 3 ms (784.2 KiB/s) ## Executing script at 05ff0000 crc32+ Trying to boot Linux from device mmc0 Found kernel in mmc0 13661579 bytes read in 979 ms (13.3 MiB/s) ## Loading kernel (any) from FIT Image at 02000000 ... Using 'board-0' configuration Verifying Hash Integrity ... OK Trying 'kernel' kernel subimage Description: Linux Kernel Type: Kernel Image Compression: lzma compressed Data Start: 0x020000dc Data Size: 10439444 Bytes = 10 MiB Architecture: AArch64 OS: Linux Load Address: 0x06000000 Entry Point: 0x06000000 Hash algo: crc32 Hash value: 0ccd8e20 Verifying Hash Integrity ... crc32+ OK ## Loading fdt (any) from FIT Image at 02000000 ... Using 'board-0' configuration Verifying Hash Integrity ... OK Trying 'fdt-0' fdt subimage Description: socfpga_socdk_vanilla Type: Flat Device Tree Compression: uncompressed Data Start: 0x029f4cd4 Data Size: 32121 Bytes = 31.4 KiB Architecture: AArch64 Hash algo: crc32 Hash value: 262d6a47 Verifying Hash Integrity ... crc32+ OK Booting using the fdt blob at 0x29f4cd4 Working FDT set to 29f4cd4 Uncompressing Kernel Image to 6000000 Loading Device Tree to 000000007ead6000, end 000000007eae0d78 ... OK Working FDT set to 7ead6000 SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256 MiB Enabling QSPI at Linux DTB... Working FDT set to 7ead6000 libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND QSPI clock frequency updated RSU: Firmware or flash content not supporting RSU RSU: Firmware or flash content not supporting RSU RSU: Firmware or flash content not supporting RSU RSU: Firmware or flash content not supporting RSU Starting kernel ... Deasserting all peripheral resets [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034] [ 0.000000] Linux version 6.12.43-altera-gd16fc609d5a7 (oe-user@oe-host) (aarch64-poky-linux-gcc (GCC) 14.3.0, GNU ld (GNU Binutils) 2.44.0.20250715) #1 SMP PREEMPT Tue Nov 25 16:06 :07 UTC 2025 [ 0.000000] KASLR disabled due to lack of seed [ 0.000000] Machine model: SoCFPGA Agilex7-M SoCDK [ 0.000000] efi: UEFI not found. [ 0.000000] earlycon: uart0 at MMIO32 0x00000000ffc02000 (options '115200n8') [ 0.000000] printk: legacy bootconsole [uart0] enabled [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000000000000, size 32 MiB [ 0.000000] OF: reserved mem: initialized node svcbuffer@0, compatible id shared-dma-pool [ 0.000000] OF: reserved mem: 0x0000000000000000..0x0000000001ffffff (32768 KiB) nomap non-reusable svcbuffer@0 [ 0.000000] NUMA: Faking a node at [mem 0x0000000000000000-0x000000017fffffff] [ 0.000000] NODE_DATA(0) allocated [mem 0x17f7fbe80-0x17f7fe4bf] [ 0.000000] Zone ranges: [ 0.000000] DMA [mem 0x0000000000000000-0x00000000ffffffff] [ 0.000000] DMA32 empty [ 0.000000] Normal [mem 0x0000000100000000-0x000000017fffffff] [ 0.000000] Movable zone start for each node [ 0.000000] Early memory node ranges [ 0.000000] node 0: [mem 0x0000000000000000-0x0000000001ffffff] [ 0.000000] node 0: [mem 0x0000000002000000-0x000000007fffffff] [ 0.000000] node 0: [mem 0x0000000100000000-0x000000017fffffff] [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x000000017fffffff] [ 0.000000] cma: Reserved 32 MiB at 0x000000007ca00000 on node -1 [ 0.000000] psci: probing for conduit method from DT. [ 0.000000] psci: PSCIv1.1 detected in firmware. [ 0.000000] psci: Using standard PSCI v0.2 function IDs [ 0.000000] psci: MIGRATE_INFO_TYPE not supported. [ 0.000000] psci: SMC Calling Convention v1.5 [ 0.000000] percpu: Embedded 25 pages/cpu s61784 r8192 d32424 u102400 [ 0.000000] Detected VIPT I-cache on CPU0 [ 0.000000] CPU features: detected: ARM erratum 845719 [ 0.000000] alternatives: applying boot alternatives [ 0.000000] Kernel command line: earlycon panic=-1 root=/dev/mmcblk0p2 rw rootwait [ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear) [ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear) [ 0.000000] Fallback order for Node 0: 0 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1048576 [ 0.000000] Policy zone: Normal [ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off [ 0.000000] software IO TLB: area num 4. [ 0.000000] software IO TLB: mapped [mem 0x0000000078a00000-0x000000007ca00000] (64MB) [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1 [ 0.000000] rcu: Preemptible hierarchical RCU implementation. [ 0.000000] rcu: RCU event tracing is enabled. [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=512 to nr_cpu_ids=4. [ 0.000000] Trampoline variant of Tasks RCU enabled. [ 0.000000] Tracing variant of Tasks RCU enabled. [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. [ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4 [ 0.000000] RCU Tasks: Setting shift to 2 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=4. [ 0.000000] RCU Tasks Trace: Setting shift to 2 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=4. [ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 [ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention. [ 0.000000] timer_probe: no matching timers found [ 0.000000] Kernel panic - not syncing: Unable to initialise architected timer. [ 0.000000] CPU: 0 UID: 0 PID: 0 Comm: swapper/0 Not tainted 6.12.43-altera-gd16fc609d5a7 #1 [ 0.000000] Hardware name: SoCFPGA Agilex7-M SoCDK (DT) [ 0.000000] Call trace: [ 0.000000] dump_backtrace.part.0+0xd4/0xe0 [ 0.000000] show_stack+0x18/0x30 [ 0.000000] dump_stack_lvl+0x60/0x80 [ 0.000000] dump_stack+0x18/0x24 [ 0.000000] panic+0x168/0x360 [ 0.000000] time_init+0x30/0x50 [ 0.000000] start_kernel+0x544/0x6d0 [ 0.000000] __primary_switched+0x80/0x88Support Request to Debug Signal Tap Issue with SoC Based Design(GHRD) on Agilex-7 FPGA
Hi Altera Support Team, Greetings from Logic Fruit Technologies. This is Bhanu Pratap and I am working on the project in which we are using Agilex-7 SOC FPGA. Goal: Utilize Agiliex-HPS's capability on a Linux OS to control dynamic features of IP Cores at runtime. Problem Statement: We are facing an issue detecting SignalTap with SoC-based designs for runtime debugging while it's enabled and added from the Quartus project to generate the programming file. Brief Description: We are using Quartus 2025.1.1 and Altera's Agilex-7 Devkit(DKSIAAGI027FA: Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit -> 4x F-Tile, Rev C). We downloaded the base GHRD design from Altera's GitHub webpage for the corresponding Quartus version. We are following each step to test GHRD and build generation for the Linux OS. We are using HPS First booting mode, we generated the build without modification and tested it. It's working fine according to the GSRD user guide. We have added a custom AXI4 Slave based CSR module to the HSP Lightweight bus to test basic register read/write using Platform Designer. We regenerated the build and re-tested but we are not getting the expected results so we added SignalTap for debugging. Build is generated using the STP file, programmed, and the OS is booting but it's not detecting SignalTap. This looks more like a process gap. We seek your support to fix this issue. Note: If we use an FPGA design without HPS, we are able to add and detect SignalTap. Seeking for urgent support. Thanks Bhanu PratapAgilex 5E ES Memory Performance Issues
Setup We observed significant performance issues during sequential memory reads in HPS. Target device is A5ED065BB32AE6SR0 from the premium dev kit using the GSRD Example. Sysbench was used to benchmark the memory performance. Test Results For comparison, we also performed the test on an STM32 system (Arm Dual Cortex-A7 800 MHz) and the host PC (Ryzen 7 CPU). Agilex 5E ES STM32MP157F Host PC, Ryzen 7 T0 (sequential read) 480 MiB/s 290 MB/s 78972 MiB/s T1 (sequential write) 4058 MiB/s 190 MB/s 44749 MiB/s T2 (random read) 67 MiB/s 373 MB/s 3461 MiB/s T3 (random write) 52 MiB/s 372 MB/s 3608 MiB/s The test cases where executed as follows: T0: sysbench --num-threads=1 --time=10 memory --memory-block-size=4MiB --memory-total-size=64GiB --memory-access-mode="seq" --memory-hugetlb=off --memory-oper=read run T1: sysbench --num-threads=1 --time=10 memory --memory-block-size=4MiB --memory-total-size=64GiB --memory-access-mode="seq" --memory-hugetlb=off --memory-oper=write run T2: sysbench --num-threads=1 --time=10 memory --memory-block-size=4MiB --memory-total-size=64GiB --memory-access-mode="rnd" --memory-hugetlb=off --memory-oper=read run T3: sysbench --num-threads=1 --time=10 memory --memory-block-size=4MiB --memory-total-size=64GiB --memory-access-mode="rnd" --memory-hugetlb=off --memory-oper=write run Observations The sequential read operation on the Agilex 5 is significantly (factor 10!) slower than the write operation. Especially when comparing to other systems where the sequential read achieves about a third more throughput. Sequential Read vs. Write: The sequential read operation on Agilex 5E ES is about 10x slower than the sequential write operation. On other systems, sequential read typically achieves about 30% higher throughput than write. We found 2 possible issues with the ES devices in the Errata: Degraded HPS EMIF performance with 2MB L3 Cache: https://docs.altera.com/r/docs/825514/current/agilextm-5-es-device-errata-and-user-guidelines/degraded-hps-emif-performance-with-2mb-l3-cache HPS EMIF read throughput less than target: https://docs.altera.com/r/docs/825514/current/agilextm-5-es-device-errata-and-user-guidelines/hps-emif-read-throughput-less-than-target The workaround for 1. is to change the L3-cache to a value different to 2MB. However, this did not improve the performance any way. For the second errata entry, there is no workaround. Question Is the "HPS EMIF read throughput less than target" errata entry the primary cause of the degraded sequential read performance? If confirmed, is this issue resolved in the series Agilex 5 Devices, and what performance improvements can we expect?
