Why are the peripherals under 2GB Peripheral Region still cached by the Nios® V/g processor?
Description Due to a problem in the: Quartus® Prime Pro Edition Software version 23.1, 23.2, 23.3, 23.4, 24.1, 24.2, 24.3, 24.3.1, 25.1 Quartus® Prime Standard Edition Software version 23.1, 24.1 The Nios® V/g processor still caches the peripherals if they are placed under a Peripheral Region that is configured to 2GB, regardless of the Base Address. This is due to a problem in the processor RTL failing to correctly implement the 2GB Peripheral Region. Other Peripheral Region sizes are not affected; only 2GB is affected. Resolution To work around this problem, please select other Peripheral Region sizes except 2GB. The Nios® V/g processor still offers Peripheral Region sizes ranging from 64KB to 1GB. The 2GB Size option for Nios® V/g processor Peripheral Region is removed beginning with the Quartus® Prime Pro Edition Software version 25.1.1 and Quartus® Prime Standard Edition Software version 25.1. Related Article NIOS V/g - peripherals under 2GB Peripheral Region | Altera Community - 350829
Why do I see an Quartus® Logic Generation Error when configuring the F-tile PMA/FEC Direct PHY IP as FGT, PMA Clocking mode, 16-bit PMA interface?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3.1 and earlier, you will see a Logic Generation Error when configuring the F-tile PMA/FEC Direct PHY IP as FGT, PMA Clocking mode, 16 bit PMA interface and placed in 200G Hard IP. The Quartus Logic Generation Error message might be similar to one of the followings: Error(22144) Error(22658) Error(21843) Resolution There is no plan to fix this problem. To work around this error, you can take one of the below two methods: Change the clocking mode from PMA clocking mode to System PLL clocking mode, or Change the F-Tile placement from 200G Hard IP to 400G Hard IP.Why does an error occur when upgrading Ethernet designs that use F‑Tile Ethernet Hard IP from Quartus® Prime Pro Edition version 22.4 or earlier to version 25.3.1?
Description Due to an issue in Quartus® Prime Pro Edition software version 22.4 and earlier, an error may be encountered when upgrading Ethernet designs created with F‑Tile Ethernet Hard IP to version 25.3.1. Error: ex_100G.eth_f_0: "Custom Ethernet line rate" (CUSTOM_RATE_GUI) 25.78125 is out of range: 10.3125-17.4 This problem is observed because the maximum supported line rate for the “Custom Ethernet line rate” was incorrectly changed to 17.4 Gbps. Resolution One workaround using the F‑Tile Ethernet Hard IP GUI is to open the .ip file, change the Ethernet mode to a different data rate, and then reconfigure it back to the original data rate. Alternatively, edit the .ip file directly by locating CUSTOM_RATE_GUI and changing its value from 25.78125 to 10.3125 Gbps. This issue is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.What Agilex™ 7 FPGA configuration scheme should be used to ensure that the PCI Express* link active time of 120ms is met?
Description To meet the PCIe* spec requirement of 120 ms, the PCIe* REFCLK needs to be running prior to configuring the device, you must specify the OSC_CLK_1 pin as 25 MHz, 100 MHz, or 125 MHz, and use AS x4 Fast Mode configuration with an AS_CLK clock set to 166 MHz. Note: For PCIe designs including Configuration via Protocol (CvP), Altera recommends you to use Micron* QSPI flash in order to load the initial configuration firmware faster to meet the PCIe wake up time for host enumeration. This is because boot ROM reads the initial configuration firmware using x4 mode when using the Micron QSPI flash. For a non-Micron flash, the boot ROM reads the firmware using x1 mode. If you need to use the non-Micron QSPI flash for PCIe design, Altera recommends you to assert PERST# signal low for a minimum of 200 ms from the FPGA POR to ensure the PCIe end point enters link training state before PERST# is deasserted. This should be considered for closed-systems only. Agilex™ 7 FPGA Device Configuration via Protocol (CvP) Implementation User Guide Related IP Cores F-Tile Avalon® Streaming IP for PCI Express* Multi Channel DMA FPGA IP for PCI Express* P-Tile Avalon® Streaming IP for PCI Express* R-Tile Avalon® Streaming IP for PCI Express* AXI Streaming IP for PCI Express* AXI Multichannel DMA IP for PCIe*Why does GD55LB02GE QSPI flash fail in Linux* in FPGA SoC device?
Description If you use Linux* version between socfpga-6.0 and socfpga-6.12.43-lts with GD55LB02GE QSPI flash, you may fail to mount the file system in Linux if it’s stored in GD55LB02GE. This is caused by the gigadevice.c in these versions. Resolution This issue is fixed in socfpga-6.12.43-lts and afterwards. You can upgrade Linux source code to this version, or comment out the GD55LB02GE entry in gigadevice.c in old versions.Why do I see compilation failure in the design using F-tile Ethernet Hard IP at 25GE-1 variant for non-MAC PCS direct mode with Firecode FEC enabled in the Quartus® Prime Pro Edition software version 25.3?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3, you may see compilation failure in the design using F-tile Ethernet Hard IP at 25GE-1 variant for non-MAC PCS direct mode with Firecode FEC enabled. This is because the Firecode FEC isn’t supported in F-tile Ethernet Hard IP at 25GE-1 variant for non-MAC PCS direct mode. Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition software version 25.3.1.Why does the Timing Analyzer report an unconstrained clock on the internal state signal when using the Generic Serial Flash Interface IP?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.1.1 and earlier, you might see that the Timing Analyzer report an unconstrained clock on the internal state signal below, when using the Generic Serial Flash Interface (GSFI) IP. <instance_path>|intel_generic_serial_flash_interface_top_0|serial_flash_inf_cmd_gen_inst|state[0] Adding a create_generated_clock constraint removes the unconstrained clock report but introduces setup timing violations because the clock relationship is inferred as zero, making timing closure unachievable in Quartus® Prime Pro Edition Software version 25.1.1. Resolution There is no reliable SDC-based workaround to achieves timing closure; adding create_generated_clock can lead to setup violations due to a zero clock relationship. This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 25.3.Why does downloading ELF file into Nios® V/g processor fail when disabled branch prediction, while enabled instruction cache?
Description Due to a problem in the Quartus ® Prime Pro Edition Software version 25.3.1, downloading ELF file into Nios ® V/g processor might fail when both the conditions below are fulfilled. Branch prediction is disabled, and Instruction cache is enabled The niosv-download command returns the error message below. Unexpected vCont reply in non-stop mode: E30 ERROR: GDB failed. This is because there is an RTL bug in the instruction cache related to its reset state. Resolution To work around this problem in the Quartus ® Prime Pro Edition Software version 25.3.1, Either enable branch prediction, Or disable instruction cache This problem is scheduled to be fixed in a future release of the Quartus ® Prime Pro Edition Software version 26.1.Why doesn’t the CDR lock signal assert in simulation for some F Tile Ethernet Hard IP variants when using Questa*–Altera® FPGA Edition in the Quartus® Prime Pro Edition software version 25.3.1?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3.1, you may see simulation failure that CDR lock signal doesn’t assert for some F‑Tile Ethernet Hard IP variants when using Questa*–Altera® FPGA Edition. Resolution There is no workaround currently. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro edition software.Why is there "sopcinfo2swinfo.exe: command not found" when running sopc-create-header-files under WSL, or Docker under Windows?
Description An error message like this: sopc-create-header-files: line 182: sopcinfo2swinfo.exe: command not found sopc-create-header-files: sopcinfo2swinfo.exe --input=./peripheral_subsys.sopcinfo --output=/tmp/sopc-create-header-files.1312.tmp.swinfo failed will be seen in the Quartus ® Prime Pro Edition Software version 25.3.1 and earlier, when using the sopc-create-header-files script within the Linux version of the Quartus ® Prime Pro Edition Software, running on the Microsoft* Windows operating system. The Linux version of the tools can be installed under Windows* using WSL, WSL2 or Docker. In all of these cases, the sopc-create-header-files script detects that it is running under Windows* and looks for an internal tool with the suffix “.exe”. However, since the Linux version has been installed, the tool does not have that suffix and so cannot be found by the sopc-create-header-files script. Resolution To work around the problem, either switch to using a Windows* installation of the Quartus® Prime Pro Edition Software, or follow these steps to continue using the Linux installation under Windows*: Under Linux, use the command “which sopc-create-header-files” to find the location of the script. Copy the script from this location to another location of your choice. Make the newly copied script version writable using the command: chmod +w <path to newly copied script> Modify your newly copied script version. Find the following line: windows_exe=.exe and either remove it or add a single # symbol at the start to comment it Use your newly modified version of the script instead of the installed version. This will now execute correctly.