Setup slack violations?
Hi, I have a design implemented in a Cyclone 10LP device, but I am struggling a bit with the Timing Analyzer. I am using Quartus Prime Lite edition 24.1. The setup-slack is violated for a number of paths, but I need some help interpreting the waveform shown in the attachment. And, looking at the path in Technology Map viewer I also struggle on how to improve the timing. How can I attack the issue? A pointer to relevant documentation is highly appreciated
TimeQuest Question Relating PLL
I have a design on a DE23-lite board. I use the onboard 50 MHz clock to feed a PLL set to 150 MHz. All registers clock on the PLL. I_clk is the 50 MHz clock. I use the following rule: create_generated_clock -name clk_pll -source [get_ports {I_clk}] -multiply_by 3 [get_pins {pll0|iopll_0|tennm_ph2_iopll|out_clk[0]}] (Yes, the PLL output has that name) Now TimeQuest complains: No paths exist between clock target "pll0|iopll_0|tennm_ph2_iopll|out_clk[0]" of clock "clk_pll" and its clock source. Assuming zero source clock latency. So I looked up the PLL input clock. But if I write: create_generated_clock -name clk_pll \ -source [get_pins {pll0|iopll_0|tennm_ph2_iopll|ref_clk0}] \ -multiply_by 3 \ [get_pins {pll0|iopll_0|tennm_ph2_iopll|out_clk[0]}] the setup slack on I_clk is -7 ns, but no register clocks on this clock. So what to do?Timing Violations: 8x F-Tile ETH Hard IP TX_CLKOUT
Hello Intel Team, In our design, we instantiated eight 10G F-Tile Ethernet Hard IPs (including ANLT) using the VHDL "GENERATE" construct. During timing analysis, we are encountering setup and hold violations on the "TX_CLKOUT" path of the F-Tile transceivers. The "REPORT_CLOCKS" command shows that these 8 clocks are being generated with a frequency of 402.83 MHz under the following names: gen_eth[0].proc_ftile_eth_hardip|eth_f_0|tx_clkout|ch23 gen_eth[1].proc_ftile_eth_hardip|eth_f_0|tx_clkout|ch22 ... gen_eth[7].proc_ftile_eth_hardip|eth_f_0|tx_clkout|ch16 The corresponding master clocks are: gen_eth[0].proc_ftile_eth_hardip|eth_f_0|tx_pld_pcs_clk_reg|ch23 TX_CLKOUT clocks are asynchronous to each other and operate independently. Therefore, we attempted to exclude them from timing analysis using the "set_clock_groups -asynchronous" constraint, like this: set_clock_groups -asynchronous \ -group { [get_clocks {gen_eth[0].proc_ftile_eth_hardip|eth_f_0|tx_clkout|ch23}] } \ -group { [get_clocks {gen_eth[1].proc_ftile_eth_hardip|eth_f_0|tx_clkout|ch22}] } \ -group { [get_clocks {gen_eth[2].proc_ftile_eth_hardip|eth_f_0|tx_clkout|ch21}] } \ -group { [get_clocks {gen_eth[3].proc_ftile_eth_hardip|eth_f_0|tx_clkout|ch20}] } \ -group { [get_clocks {gen_eth[4].proc_ftile_eth_hardip|eth_f_0|tx_clkout|ch19}] } \ -group { [get_clocks {gen_eth[5].proc_ftile_eth_hardip|eth_f_0|tx_clkout|ch18}] } \ -group { [get_clocks {gen_eth[6].proc_ftile_eth_hardip|eth_f_0|tx_clkout|ch17}] } \ -group { [get_clocks {gen_eth[7].proc_ftile_eth_hardip|eth_f_0|tx_clkout|ch16}] } However, this approach results in the following errors: - Warning(20314): Invalid collection filter: [get_clocks {gen_eth[0].proc...}] - Warning(332049): Ignored set_clocks_group: Argument -group with value could not match any element of the type clk. - Warning(332049): Argument -group is not an obejct ID. I’ve tried multiple approaches, get_nets, Get_pins, also using wildcards and "create_generated_clock", but nothing has resolved the issue. According to my understanding, a "create_generated_clock" constraint shouldn't be necessary, since these clocks are automatically generated by Quartus. When inspecting the design in the Timing Analyzer using "get_clocks *ch23, the clock names appear to be internally resolved to autogenerated IDs like "_co15660". However, these IDs are not stable and may change with each compile (fit), which makes them unsuitable for constraints. At this point, I am running out of ideas. Question: How can I properly constraint or eliminate the setup and hold violations on the eight "TX_CLKout" clocks generated by Quartus in the F-Tile Ethernet Hard IPs? Should I just use "Set_False_Path"? I used the "Generate" command in VHDL to instantiate the 8 F-Tile ETH Hard IP + 8 ANLT. Could be this a problem ? kind regards Jacob
Quartus Prime Pro 25.1.0 Reports Unconstrained Paths in Cyclone 10GX PCIe Hard IP
Hi, Recently I have installed Quartus Prime Pro 25.1.0 and recompiled a Cyclone 10GX design that was originally compiled in Quartus Prime Pro 20.1.0. All IP's were updated automatically in 25.1.0. The Timing Analyzer reports Illegal Clocks and Unconstrained Clocks within the PCIe Hard IP. Those errors are not reported in 20.1.0. Are they genuine errors? Can they be ignored? Many thanks Wei
Cyclone 10 SERDES Receiver Timing Constraints
Hello, I am trying to send some data serially over a very simple SERDES interface made of a single LVDS clock and data going from FPGA 1 to FPGA 2. In the receiver FPGA (FPGA 2), I want to use SERDES without DPA. My LVDS_CLK is running at 50MHz. The SERDES factor is 8. Therefore my LVDS_DIN rate is 400MHz (50MHz * 😎 I am confused about how to do the timing constraints exactly. I tried to set the input delays using the following : METHOD 1 : create_clock -name LVDS_CLK_VIRTUAL -period 20 create_clock -name LVDS_CLK -period 20 [get_ports {LVDS_CLK}] set_input_delay -clock { LVDS_CLK_VIRTUAL } -min 0 [get_ports {LVDS_DIN[0]}] set_input_delay -clock { LVDS_CLK_VIRTUAL} -max 0.5 [get_ports {LVDS_DIN[0]}] set_input_delay -clock { LVDS_CLK_VIRTUAL} -min 0 [get_ports {LVDS_DIN[0]}] -add -clock_fall set_input_delay -clock { LVDS_CLK_VIRTUAL} -max 0.5 [get_ports {LVDS_DIN[0]}] -add -clock_fall Timing quest timing analyser does not use my delay value assigned using set_input_delay constraints for some reason. I checked the list of ignored constraints in Timing Quest, but this list was empty, so it was happy with the assignments - just hasnt used them for some reason. Also, I am not even sure if this method works, as my input clock is only going at 50MHz, while my data is changing at 400MHz. I am not sure if my input delay constraint should be using the virtual clock as I have done here. Method 2 : In the IP wizard for the LVDS SERDES, there is this RCCS setting in the Receiver Settings tab. Is the correct way to configure the input delay using this RCCS value (and not the SET_INPUT_DELAY constraint)? If so, how does this account for the min and max delay settings? Don't I need two separate settings for the SETUP and HOLD timings to be verified? Any input is highly appreciated! Best regards, LakUnderstanding timing constraints in timing analyzer
Hi all, I am quite new to timing constraints. I took an example code to understand and apply the constraints from FPGA Academy website. https://fpgacademy.org/tutorials.html Using the Quartus Prime Timing Analyzer VHDL code. I am using Quartus prime lite 24.1 edition. FPGA 10M08DAF484C8G. I dont have any board. As per tutorial i have added this constraint. 4ns = 250mhz clock Still there is setup violations. How can i solve this? I reduced the clock from 250 to 125 then the violation disappered. What if i had a clock osc from outside the board with fixed 250mhz? Then how would i resolve the violations? How to remove unconstrained i/o port paths also? Any example codes, tutorials, explanation will be grateful. Thank you
Timing Violations in JTAG Signals
Hello, I have a Arria10 FPGA design using Platform Desginer which includes a Avalon to JTAG Brdige. I have added a jtag.sdc file to the project based on this guideline: JTAG Signals and set all the "--customize here--" sections according to my design (see attached sdc file). However the Timing Analyzer gives me several setup violations on JTAG signals: -18.207 auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_8 altera_reserved_tdo altera_reserved_tck (INVERTED) altera_reserved_tck (INVERTED) 33.333 -2.582 4.240 Slow 950mV 100C Model -18.206 auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_9 altera_reserved_tdo altera_reserved_tck (INVERTED) altera_reserved_tck (INVERTED) 33.333 -2.582 4.239 Slow 950mV 100C Model -18.157 auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_7 altera_reserved_tdo altera_reserved_tck (INVERTED) altera_reserved_tck (INVERTED) 33.333 -2.582 4.190 Slow 950mV 100C Model -18.142 auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_10 altera_reserved_tdo altera_reserved_tck (INVERTED) altera_reserved_tck (INVERTED) 33.333 -2.582 4.175 Slow 950mV 100C Model -18.123 auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_11 altera_reserved_tdo altera_reserved_tck (INVERTED) altera_reserved_tck (INVERTED) 33.333 -2.582 4.156 Slow 950mV 100C Model -18.120 auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_6 altera_reserved_tdo altera_reserved_tck (INVERTED) altera_reserved_tck (INVERTED) 33.333 -2.582 4.153 Slow 950mV 100C Model -17.207 auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_1 altera_reserved_tdo altera_reserved_tck (INVERTED) altera_reserved_tck (INVERTED) 33.333 -2.125 3.697 Slow 950mV 0C Model -17.136 auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_3 altera_reserved_tdo altera_reserved_tck (INVERTED) altera_reserved_tck (INVERTED) 33.333 -2.125 3.626 Slow 950mV 0C Model -17.069 auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_2 altera_reserved_tdo altera_reserved_tck (INVERTED) altera_reserved_tck (INVERTED) 33.333 -2.125 3.559 Slow 950mV 0C Model -17.064 auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_4 altera_reserved_tdo altera_reserved_tck (INVERTED) altera_reserved_tck (INVERTED) 33.333 -2.125 3.554 Slow 950mV 0C Model -16.972 auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM altera_reserved_tdo altera_reserved_tck (INVERTED) altera_reserved_tck (INVERTED) 33.333 -2.125 3.462 Slow 950mV 0C Model -16.075 auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|atom_inst|atom~jtag_reg__nff altera_reserved_tdo altera_reserved_tck (INVERTED) altera_reserved_tck (INVERTED) 33.333 -0.450 4.240 Slow 950mV 0C Model The listed registers look similar but not identical to the security reg listing in the jtag.sdc line 86-89 which are to be ignored. So I'm not sure if these errors are actual errors caused, e.g. by a too high JTAG clock rate, or if these registers are just missing a respective false path due to encrypted core. The Timing Analyzer does list the falling paths as encrypted: Please advise how to deal with these JTAG signal in timing analysis. Thanks FabianDoes Max 10 need "derive_pll_clocks" in constraint file
Below is from "Quartus® Prime Pro Edition User Guide": Note: Only Arria 10 and Cyclone® 10 GX devices support the Derive PLL Clocks (derive_pll_clocks) constraint. For all other supported devices, the Timing Analyzer automatically derives PLL clocks from constraints bound to the related IP. Appreciate if any one can confirm that for MAX 10 series we do not need to have "derive_pll_clocks" in the constraint file according to above statement in the user guide.
Restricted Fmax due to minimum period
I have created a simple project with a 500 MHz clock fed into a clock pin set for LVDS. This clock goes only to a divide-by-4 block (two flip-flops) and the resulting 125 MHz is fed to an output pin. If I compile this for a Cyclone10LP (10CL006YE144) with speed grade C8, the timing analyzer says that Fmax is 866.5 MHz but restricted Fmax is 402.09 MHz (due to minimum period restriction), for Slow 1200mV 100C Model. This somewhat correlates to table 20 about clock tree performance, in the Cyclone 10 LP device datasheet, which specifies max 402 MHz. I cannot find any definition about this "clock tree performance" so I guess it is just a "stay safe and keep below"-value used by Quartus for max frequency regardless of calculated setup and hold times. Changing to a device with speed grade A7, I get Fmax at 939.85 MHz and restricted Fmax at 402.09 MHz. I don't understand why the first value now is higher, but the latter still correlates with table 20 that states 402 MHz for A7. Changing to speed grade I7, I get Fmax at 961.54 MHz and restricted Fmax at 403.06 MHz. Now this does not correlate with table 20, that states 437.5 MHz max for I7. And for C6, I get Fmax at 1112.35 MHz and restricted Fmax at 438.02 - not the 500 MHz stated in table 20. How should this be understood?
