Timing Violations: 8x F-Tile ETH Hard IP TX_CLKOUT

Hello Intel Team,

In our design, we instantiated eight 10G F-Tile Ethernet Hard IPs (including ANLT) using the VHDL "GENERATE" construct. During timing analysis, we are encountering setup and hold violations on the "TX_CLKOUT" path of the F-Tile transceivers.

The "REPORT_CLOCKS" command shows that these 8 clocks are being generated with a frequency of 402.83 MHz under the following names:

gen_eth[0].proc_ftile_eth_hardip|eth_f_0|tx_clkout|ch23
gen_eth[1].proc_ftile_eth_hardip|eth_f_0|tx_clkout|ch22
...
gen_eth[7].proc_ftile_eth_hardip|eth_f_0|tx_clkout|ch16

The corresponding master clocks are:

gen_eth[0].proc_ftile_eth_hardip|eth_f_0|tx_pld_pcs_clk_reg|ch23

TX_CLKOUT clocks are asynchronous to each other and operate independently. Therefore, we attempted to exclude them from timing analysis using the "set_clock_groups -asynchronous" constraint, like this:

set_clock_groups -asynchronous \
-group { [get_clocks {gen_eth[0].proc_ftile_eth_hardip|eth_f_0|tx_clkout|ch23}] } \
-group { [get_clocks {gen_eth[1].proc_ftile_eth_hardip|eth_f_0|tx_clkout|ch22}] } \
-group { [get_clocks {gen_eth[2].proc_ftile_eth_hardip|eth_f_0|tx_clkout|ch21}] } \
-group { [get_clocks {gen_eth[3].proc_ftile_eth_hardip|eth_f_0|tx_clkout|ch20}] } \
-group { [get_clocks {gen_eth[4].proc_ftile_eth_hardip|eth_f_0|tx_clkout|ch19}] } \
-group { [get_clocks {gen_eth[5].proc_ftile_eth_hardip|eth_f_0|tx_clkout|ch18}] } \
-group { [get_clocks {gen_eth[6].proc_ftile_eth_hardip|eth_f_0|tx_clkout|ch17}] } \
-group { [get_clocks {gen_eth[7].proc_ftile_eth_hardip|eth_f_0|tx_clkout|ch16}] }

However, this approach results in the following errors:

- Warning(20314): Invalid collection filter: [get_clocks {gen_eth[0].proc...}]

- Warning(332049): Ignored set_clocks_group: Argument -group with value could not match any element of the type clk.

- Warning(332049): Argument -group is not an obejct ID.

I’ve tried multiple approaches, get_nets, Get_pins, also using wildcards and "create_generated_clock", but nothing has resolved the issue.

According to my understanding, a "create_generated_clock" constraint shouldn't be necessary, since these clocks are automatically generated by Quartus.

When inspecting the design in the Timing Analyzer using "get_clocks *ch23, the clock names appear to be internally resolved to autogenerated IDs like "_co15660".

However, these IDs are not stable and may change with each compile (fit), which makes them unsuitable for constraints.

At this point, I am running out of ideas.

• Question:
  How can I properly constraint or eliminate the setup and hold violations on the eight "TX_CLKout" clocks generated by Quartus in the F-Tile Ethernet Hard IPs?
• Should I just use "Set_False_Path"?
• I used the "Generate" command in VHDL to instantiate the 8 F-Tile ETH Hard IP + 8 ANLT. Could be this a problem ?

kind regards

Jacob