Hello,
- Run report_clocks in the Timing Analyzer GUI.
- Identify the actual clock names for your 8 TX_CLKOUT clocks.
- Update your SDC to use the internal names (e.g., _co15660, etc.) in your set_clock_groups constraint.
- Re-run Timing Analysis.
- The violations should be gone for cross-domain paths.
- If you want a more robust SDC that survives name changes, use wildcards or regular expressions if possible, or group all relevant clocks at once:
- set_clock_groups -asynchronous -group [get_clocks *_tx_clkout*]
I used the "Generate" command in VHDL to instantiate the 8 F-Tile ETH Hard IP + 8 ANLT. Could be this a problem ?
- No, the VHDL generate statement is not the problem as long as each instance is independent. The issue is the SDC matching, not your VHDL instantiation.
Hope this helps.
Regards,
Pavee
New Contributor
