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JackDalton
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4 months ago

Timing Violations: 8x F-Tile ETH Hard IP TX_CLKOUT

Hello Intel Team, In our design, we instantiated eight 10G F-Tile Ethernet Hard IPs (including ANLT) using the VHDL "GENERATE" construct. During timing analysis, we are encountering setup and hold v...
Hdl
Simulation
Timing
JackDalton's avatar
JackDalton
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4 months ago

Hello,

is the problem perhaps too obvious ?

The F-Tile manual couldn't give me any clues.

What have I missed?

I would appreciate a quick hint.

I would also like to add that we are using the Agilex 7 i-series with Quartus 25.1.

kind regards

Jack