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JackDalton's avatar
JackDalton
Icon for New Contributor rankNew Contributor
1 year ago

Timing Violations: 8x F-Tile ETH Hard IP TX_CLKOUT

Hello Intel Team, In our design, we instantiated eight 10G F-Tile Ethernet Hard IPs (including ANLT) using the VHDL "GENERATE" construct. During timing analysis, we are encountering setup and hold v...
Hdl
Simulation
Timing
paveetirrasrie_Altera's avatar
paveetirrasrie_Altera
Icon for Frequent Contributor rankFrequent Contributor
1 year ago

Hello,


We do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support.

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