Validating ECC Functionality on Custom Agilex 5 SOM in Linux Kernel
We are now looking to validate ECC (Error Correction Code) functionality on our custom Agilex 5 System-on-Module (SOM) running Linux. Our objective is to ensure that ECC is correctly enabled and functioning across all relevant memory regions, and that error detection and correction mechanisms are properly integrated at the kernel level. Could you please provide guidance on the necessary kernel configurations, device tree modifications, and available tools or procedures to test and monitor ECC behavior on this platform? Any documentation or reference designs specific to Agilex 5 ECC support would be highly valuable.To evaluate and monitor CPU frequency behavior in the Kernel OS
We need to verify CPU frequency behaviour straight from the Linux kernel because we are currently working with a customised Agilex 5 System-on-Module (SOM). Ensuring appropriate frequency scaling and governor functionality under a range of workloads is our aim. Would you kindly provide guidance regarding the device tree modifications, kernel configurations, and testing methods needed to enable and validate CPU frequency scaling on this platform? I would be very grateful for any advice or reference materials that are specific to Agilex 5.
25.3 PRO Release
Version: Release 25.3 PRO Quartus Build/TAG: B109/QPDS25.3_REL_GSRD_PR Release Date: October 10, 2025 Device Affected: Agilex™ 3, Agilex™ 5, Agilex™ 7, Startix® 10, Arria® 10 Release Type: Major release/Binary release Binary Release Path: http://releases.rocketboards.org/2025.10/ Major Features Released Support of GHRD 2.0 in Agilex™ 5 which includes foundational boot to Linux, ability to create compatible phase 2 bitstreams, parameterized HPS for maximum performance and best practices. Support of GSRD 2.0 Yocto layers for the Agilex 5 E-Series Premium DevKit with OOBE daughtercard for the GHRD 2.0 baseline design. Agilex 5 GSRD Development User Experience Improvement through KAS using a graphical/text interface to configure a limited number of high-level options on top of simplified Yocto recipes. - GSRD 2.0 with Kas Build System Support for running Agilex 5 Simics Simulation under the GSRD 2.0 framework. Booting from SD Card and QSPI is supported. - Exercising Simics Simulation from GSRD 2.0 Support GHRD and GSRD for Agilex™ M-Series PRQ HBM2e for DK-Sl-AGM039EA development kit. The GSRD is capable of booting to Linux. - Build the GSRD for DK-DEV-AGM039EA Hypervisor Multi-OS Support Example, demonstrating Linux and Zephyr running side-by-side in the HPS cluster. - HPS Xen Hypervisor GSRD System Example Design: Agilex™ 3 FPGA and SoC C-Series Development Kit Support for monitoring of SEU errors from the SDM in the HPS in Agilex™ 7. Add capability to measure the latency of Linux SMC calls. Support Nios V Lockstep application with a fail-safe mechanism
Unable to access rocketboards.org
Hi, I am currently unable to access the www.rocketboards.org website. I need it for multiple purposes related to the use of the GSRD for cyclone 5, namely it is accessed by the image build script. Any information as to why the website is no longer working and when it might be available again? Thanks!
FPGA-HPS DDR contention on Agilex5 SoC while running Linux: efficient data exchange strategies
I’m working on a device based on an Agilex5 SoC with HPS, which is new hardware for me. The FPGA and HPS will share DDR memory, and Linux will be running on the HPS at the same time. The FPGA will be streaming a high volume of data that needs to be consumed by a userspace program on the CPU. I’m concerned that if the FPGA saturates the memory interconnect, the kernel might struggle to perform memory allocations or other transactions for other threads. Has anyone encountered this kind of bus contention on Agilex/SoC platforms? What strategies do you use to prevent FPGA traffic from starving HPS memory accesses while Linux is running? Also, is there any recommendation / strategy for an FPGA and a userspace program on Linux to exchange data efficiently and safely in this kind of setup?High-Latency Ethernet on Arria 10 SoC device using HPS EMAC and KSZ9031
Hello, I observe a strange issue using the 1Gbps Ethernet on the Arria 10 SoC HPS. I observe the issue on our custom board and also on the Arria 10 Dev Kit. For simpler debugging, explanation and potential reproducibility, I focus now on the Dev Kit: https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/arria/10-sx.html I built the Kernel 6.6 for the development board and use the tool `iperf3` for an Ethernet stress test. The setup is simple: Direct connection from the DevKit to a Computer. On the Dev Kit I start the "Server" with `iperf3 -s` and on the PC side, I call the client in bidirectional mode like this: `iperf3 -c <IP> --bidir`. In parallel I start a ping on my PC console to observe the Ethernet latency. Every now and than, the ping latency increase to 500-1000ms (after the iperf3 test has finished and no data transfer is done). It is really sporadic and doesn't happen every time. But it is some how a big issue on our product using the Arria 10 device. I think it is some how related with an old observation: https://community.intel.com/t5/Intel-SoC-FPGA-Embedded/is-there-a-bug-in-the-Ethernet-MAC-of-Arria10-SoC-devices/m-p/1238772#M866 At this time now specific answer for the issue was found. And now the issue is back after the kernel update. So whats happen here? And how can we get a stable Ethernet connection? Is there any patches or bugfixes available for the EMAC driver? Cheers SilvanMain Features Released in 25.1.1
Main Features Released in 25.1.1: Initial support of the Agilex 3 device. Released GSRD for the Agilex 3 C-Series Development Kit. Reference: https://altera-fpga.github.io/rel-25.1.1/embedded-designs/agilex-3/c-series/gsrd/ug-gsrd-agx3/ DDR ECC support in the Agilex 5. Support of production Agilex 7 F-Series Crypto device. GSRD for DK-DEV-AGF0123FA dev kit (using production AGFD023R24C2E1VC ) replaces the DK-DEV-AGF027F1ES dev kit (using engineering sample AGFB027R24C2E2VR2). Reference: https://altera-fpga.github.io/rel-25.1.1/embedded-designs/agilex-7/f-series/fpga/gsrd/ug-gsrd-agx7f-fpga/ Support of USB 3.1 in Agilex 5 GSRDs. Support of booting from eMMC in ATF to Linux Direct boot for Agilex 5 device. Reference: https://altera-fpga.github.io/rel-25.1.1/embedded-designs/agilex-5/e-series/premium/boot-examples/ug-linux-boot-agx5e-premium/#boot-from-emmc_1 Removed generation of NAND binaries in Agilex 5 GSRD. Will be re-enabled when production devices get released.Interrup numbers of Arria 10 EDAC
Hi, I try to enable the Error Detection and Correction (EDAC) for EMAC1 on my Arria 10 SoC device. I found the device tree entries for EMAC0 in the Linux kernel sources: emac0-rx-ecc@ff8c0800 { compatible = "altr,socfpga-eth-mac-ecc"; reg = <0xff8c0800 0x400>; altr,ecc-parent = <&gmac0>; interrupts = <4 IRQ_TYPE_LEVEL_HIGH>, <36 IRQ_TYPE_LEVEL_HIGH>; }; emac0-tx-ecc@ff8c0c00 { compatible = "altr,socfpga-eth-mac-ecc"; reg = <0xff8c0c00 0x400>; altr,ecc-parent = <&gmac0>; interrupts = <5 IRQ_TYPE_LEVEL_HIGH>, <37 IRQ_TYPE_LEVEL_HIGH>; }; Where do I find the interrupts used for EMAC1? Is there any documentation available? And does it require some changes in my Quartus project as well or is it fully covered by the Linux drivers?Main features released in 25.1
Main Features Released in 25.1: Agilex 5 QSPI ownership selection from Quartus to decide if SDM will keep the ownership or if the ownership could be granted to the HPS. References: https://www.intel.com/content/www/us/en/docs/programmable/814346/25-1/hps-use-of-sdm-qspi-controller-use-cases.html , Check section 4.2.1 Device and Pin Options and 4.12 QSPI Controller Ownership Selection Impact on the HPS software Agilex 5 Enable/Disable Attestation or RSU use case based on new QSPI ownership selection. References: https://www.intel.com/content/www/us/en/docs/programmable/814346/25-1/feature-availability-under-sdm-hps-ownership.html Agilex 5 Implemented IEEE-1588v2.1 (2019) time stamp features in Ethernet TSN hard IP. References: TSN - HPS RGMII System, TSN - RGMII HVIO System, TSN - SGMII XCVR System Agilex 5 Created a Reference Designs demonstrating use of SDM crypto services API from FPGA Discontinued building of GHRD for DK-SI-AGI027FA and DK-SI-AGI027FB development kits for Intel® Agilex™ I-Series Transceiver-SoC Development Kit (4x F-Tile). Provide Linux kernel support query the ATF API version through a sysfs entry. Support the SiPSVC V3 and new unified FCS client commands. Release Notes 25.1: https://github.com/altera-fpga/gsrd-socfpga/releases/tag/QPDS25.1_REL_GSRD_PR