p0_pin_perst_n remains asserted when implementing GTS AXI Streaming intel FPGA IP for PCI Express
Hi, I'm using GTS AXI Streaming intel FPGA IP for PCI Express to implement PCIe on Agilex 5 FPGA (A5ED065BB32AE4 ,Quartus Prime 25.1) . I connect Pin p0_pin_perst_n_i to a 3.3v pll up resistance on the board while pin p0_pin_perst_n_1_i is left floating . When testing on the board , p0_pin_perst_n remains asserted and the p0_reset_status_n remains low . It seems like the IP cannot jump out off reset . I wonder what may cause this situation and how can i solve the problem . I also tried to simulate the ip in Questa intel FPGA . I found that p0_pin_perst_n deasserted correctly after system PLL got locked in simulation .The simulation and the on board testing i made were using the same top module .Here is my testing project . Many thanks, Chester
onnecting the F-Tile Reference and System PLL Clock IP out_coreclk_#i port to an IOPLL FPGA IP
Hello Intel forums, I'm trying to connect a out_coreclk from an F-tile Reference and System PLL Clock IP to an IOPLL. I understand that I cannot do this directly, so I'm following the workaround described here: https://www.intel.com/content/www/us/en/support/programmable/articles/000098971.html Here is my code: clocko_blocko : block signal half_core : std_logic; component clk_ctrl is port ( inclk : in std_logic := 'X'; -- clk clock_div1x : out std_logic -- clk ); end component clk_ctrl; component pll is port ( refclk : in std_logic := 'X'; -- clk locked : out std_logic; -- export rst : in std_logic := 'X'; -- reset outclk_0 : out std_logic -- clk ); end component pll; signal half_core_iopll_ref : std_logic; signal source : std_logic; begin proc_halver : process(coreclk_feb) begin if rising_edge(coreclk_feb) then half_core <= not half_core; end if; end process proc_halver; clctrl : component clk_ctrl port map ( inclk => half_core, clock_div1x => half_core_iopll_ref ); ipll : component pll port map ( refclk => half_core_iopll_ref, locked => open, rst => rst, outclk_0 => clk_320 ); end block clocko_blocko; Unfortunately. the pll never locks. Using a firmware module, I've measured the frequency of "coreclk_feb", "half_core", and "half_core_iopll_ref" and they all have correct values, but "clk_320" has a nonsensical value. Are there particular settings needed for the Clock Control FPGA IP buffer and IOPLL FPGA IP that are not covered in the linked post? My IOPLL is set to double the input frequency to compensate for the division in the "proc_halver" process, is that a problem? I've tried this in Quartus 23.4 and 24.3.1 Cheers, Sam
CAUI‑4 reception on Agilex 5 via GTS PHY IP?
Hello, Does Agilex 5 support CAUI‑4 input for implementing a 100G Ethernet receive path? I’m working on a design where I intend to receive 100G Ethernet from a QSFP28 module, using 4 lanes at 25.78125 Gbps. According to Intel documentation, Agilex 5 transceivers support: up to 28.9 Gbps NRZ, standard PCS (64b/66b), and interfaces like XLPPI, XLAUI, etc. However, CAUI‑4 is not explicitly mentioned in Agilex 5 documentation or IP catalog, while previous devices like Arria 10 do mention it directly. I configured the GTS PMA/FEC Direct PHY IP with 4 × 25.78125 Gbps and enabled PCS (IEEE MII / PCS66). The IP compiles successfully in Quartus Pro 25.1, and simulation passes. But it’s unclear whether this configuration is officially supported, or sufficient to receive and deserialize CAUI‑4 input from QSFP28. Also, I encountered conflicting documentation: One source says PCS is not supported above 17.16 Gbps. Another states that "Ethernet mode: 4 × 10/25 GbE PCS direct mode (64b/66b hard IP)" is supported. Here are my questions: Can we implement CAUI‑4 reception manually using GTS PHY IP with PCS enabled? Is there a soft MAC IP (even licensed) available that supports this 100G aggregation for Agilex 5? Are there any Quartus 25.1 limitations for this mode we should be aware of? Thank you in advance!Agilex 5 CAUI-10, XLAUI, XLPPI Specification supported for 100G Ethernet
Hello. I'm trying to implement 100G Ethernet In Agilex™ 5 FPGAs: High-Speed Serial Interface (HSSI) Hard IP documentation states that Agilex 5 supports these specifications - CAUI-10, XLAUI, XLPPI. But in the GTS PMA/FEC Direct PHY Intel FPGA IP IP core - I can't choose 10 transceiver lines, only 8. which is not entirely clear, since to support CAUI-10 need to be able to select 10 lines. Maybe there is another way to implement CAUI-10, another core? I would like to use an external PHY to implement 100GE, but I don’t see a way to implement this in Agilex™ 5. Assuming I implement the alignment, skew compensation, and bit ordering correctly (use 10 instance GTS IP Core)— would this be a feasible way to receive a CAUI-10 stream? And if so — does it mean I could also implement CAUI-4 the same way (i.e. aggregating 4×25G manually), given that the transceivers can handle it individually?
Agilex 5 GTS Reset Sequencer Intel FPGA IP : what value to set to i_refclk_bus_out with a PCIe IP ?
Hello, Using a PCIe IP in Root Port on a AGILEX 5, I have to use the GTS Reset Sequencer Intel FPGA IP configured in PCIe. With Quartus 2025.1, the i_refclk_bus_out port appears on the GTS Reset Sequencer Intel FPGA IP. There is no port on the PCIe IP to connect to port i_refclk_bus_out. So, to which signal or to what value the port i_refclk_bus_out must be connected ? Thanks. Serge
PCIe differential REFCLK connection from M.2 connector to an Agilex 5 device
We will make a M.2-card with an Agilex 5 device and connect the M.2-card trough PCIe with the host (laptop). Is it possible to connect the REFCLKp and REFCLKn pins from a M.2 connector directly (DC coupling without any devices like capacitors) to the REFCLK_GTS1x_RXp and REFCLK_GTS1x_RXn pins of the GTS transceiver?