Can't find Agilex 7 M I/O PLL Reconfiguration Design Example
Hi, Recently updated document "Agilex™ 7 Clocking and PLL User Guide M-Series", 769001 2025.10.09 refers to a design example which uses an EMIF Calibration IP for I/O PLL reconfiguration: 6.1.7. Design Example for I/O PLL Reconfiguration I can't find this design on Intel or Altera sites. Can anyone please tell if it exists. I can find very similar Agilex 7 PLL reconfig examples but they use different calibration IP, not usable with Agilex 7M devices. I'm trying to utilize IOPLL's dynamic output phase adjustment only. This was easy with earlier generation devices as the I/O PLL provided a specific control interface for this purpose. Phase shift control port or something similar. Thanks, Ju-ti
Error: dut.p0_hip_status has no associated reset.
Hello Altera I am using Quartus Prime Pro 25.1.0 build 129 03/26/2025 SC Pro Edition. In my Agiliex 7 Design project, I have Intel R-Tile MCDMA for PCI Express intel_pcie_rtile_mcdma Version 5.3.1 Ip instantiated as "dut". in parameters settings I have enabled to have hip status interface. https://www.intel.com/content/www/us/en/docs/programmable/683821/25-1-1/hard-ip-status-interface.html this interface is connected to a custom design QCP file. The QCP uses "app_clk" and "app_nreset_status" from dut ip as its clk and reset inputs. They go through clock bridge and reset bridge. Clock and reset outputs from these bridges are used internally in custom logic code. In platform designer as I connect "dut.p0_hip_status" and "custom_module.pcie_ep_hip_status_in" ports, I get an error as following "Error: pcie_ed: Interfaces custom_module.pcie_ep_hip_status_in and dut.p0_hip_status must have matching associated resets, but dut.p0_hip_status has no associated reset." This Error does not make sense to me, as dut`s hip status interface and my qcp`s status interface ports shows correct clock and reset association in component instantiation tab; and my custom design uses same clock and reset to its clock and reset bridge inputs. can you please help me to understand what is this error about and how do i resolve it?
Please let me know how to get a GTS license for Agilex 5.
I have already some licenses, for example, IP-SDI-II, IP-DP, IP-HDMI and so on. I want to use these IP on Agilex 5. However, Ordering Code is not match the IPs I have when I searched the IP User Guide. SDI => IP-GTS-SDI-II Display Port => IP-GTS-DP Is it possible to get a License of IP-GTS-xxx, if I regenerate in my SSLC ? Or, Need I buy the new licenses for GTS Transceiver? Thanks.
ALT PLL GUI MESSDED UP ON INVOCATION
Hi All ALTERA Experts, I have a problem setting up a new PLL due to the GUI looking like the mess you can see in my attached screenshot. I am using Quartus Standard edition Version 25.1 I am on a windows 10 machine and all of the other IP GUIs seem to work fine, its just this PLL IP GUI that seems to get messed up. I am using a MAX10 FPGA. Both my PC and Graphics card are working fine. Can anybody suggest why this occurs ? Thanks, Barryp0_pin_perst_n remains asserted when implementing GTS AXI Streaming intel FPGA IP for PCI Express
Hi, I'm using GTS AXI Streaming intel FPGA IP for PCI Express to implement PCIe on Agilex 5 FPGA (A5ED065BB32AE4 ,Quartus Prime 25.1) . I connect Pin p0_pin_perst_n_i to a 3.3v pll up resistance on the board while pin p0_pin_perst_n_1_i is left floating . When testing on the board , p0_pin_perst_n remains asserted and the p0_reset_status_n remains low . It seems like the IP cannot jump out off reset . I wonder what may cause this situation and how can i solve the problem . I also tried to simulate the ip in Questa intel FPGA . I found that p0_pin_perst_n deasserted correctly after system PLL got locked in simulation .The simulation and the on board testing i made were using the same top module .Here is my testing project . Many thanks, Chester
onnecting the F-Tile Reference and System PLL Clock IP out_coreclk_#i port to an IOPLL FPGA IP
Hello Intel forums, I'm trying to connect a out_coreclk from an F-tile Reference and System PLL Clock IP to an IOPLL. I understand that I cannot do this directly, so I'm following the workaround described here: https://www.intel.com/content/www/us/en/support/programmable/articles/000098971.html Here is my code: clocko_blocko : block signal half_core : std_logic; component clk_ctrl is port ( inclk : in std_logic := 'X'; -- clk clock_div1x : out std_logic -- clk ); end component clk_ctrl; component pll is port ( refclk : in std_logic := 'X'; -- clk locked : out std_logic; -- export rst : in std_logic := 'X'; -- reset outclk_0 : out std_logic -- clk ); end component pll; signal half_core_iopll_ref : std_logic; signal source : std_logic; begin proc_halver : process(coreclk_feb) begin if rising_edge(coreclk_feb) then half_core <= not half_core; end if; end process proc_halver; clctrl : component clk_ctrl port map ( inclk => half_core, clock_div1x => half_core_iopll_ref ); ipll : component pll port map ( refclk => half_core_iopll_ref, locked => open, rst => rst, outclk_0 => clk_320 ); end block clocko_blocko; Unfortunately. the pll never locks. Using a firmware module, I've measured the frequency of "coreclk_feb", "half_core", and "half_core_iopll_ref" and they all have correct values, but "clk_320" has a nonsensical value. Are there particular settings needed for the Clock Control FPGA IP buffer and IOPLL FPGA IP that are not covered in the linked post? My IOPLL is set to double the input frequency to compensate for the division in the "proc_halver" process, is that a problem? I've tried this in Quartus 23.4 and 24.3.1 Cheers, Sam
CAUI‑4 reception on Agilex 5 via GTS PHY IP?
Hello, Does Agilex 5 support CAUI‑4 input for implementing a 100G Ethernet receive path? I’m working on a design where I intend to receive 100G Ethernet from a QSFP28 module, using 4 lanes at 25.78125 Gbps. According to Intel documentation, Agilex 5 transceivers support: up to 28.9 Gbps NRZ, standard PCS (64b/66b), and interfaces like XLPPI, XLAUI, etc. However, CAUI‑4 is not explicitly mentioned in Agilex 5 documentation or IP catalog, while previous devices like Arria 10 do mention it directly. I configured the GTS PMA/FEC Direct PHY IP with 4 × 25.78125 Gbps and enabled PCS (IEEE MII / PCS66). The IP compiles successfully in Quartus Pro 25.1, and simulation passes. But it’s unclear whether this configuration is officially supported, or sufficient to receive and deserialize CAUI‑4 input from QSFP28. Also, I encountered conflicting documentation: One source says PCS is not supported above 17.16 Gbps. Another states that "Ethernet mode: 4 × 10/25 GbE PCS direct mode (64b/66b hard IP)" is supported. Here are my questions: Can we implement CAUI‑4 reception manually using GTS PHY IP with PCS enabled? Is there a soft MAC IP (even licensed) available that supports this 100G aggregation for Agilex 5? Are there any Quartus 25.1 limitations for this mode we should be aware of? Thank you in advance!Agilex 5 CAUI-10, XLAUI, XLPPI Specification supported for 100G Ethernet
Hello. I'm trying to implement 100G Ethernet In Agilex™ 5 FPGAs: High-Speed Serial Interface (HSSI) Hard IP documentation states that Agilex 5 supports these specifications - CAUI-10, XLAUI, XLPPI. But in the GTS PMA/FEC Direct PHY Intel FPGA IP IP core - I can't choose 10 transceiver lines, only 8. which is not entirely clear, since to support CAUI-10 need to be able to select 10 lines. Maybe there is another way to implement CAUI-10, another core? I would like to use an external PHY to implement 100GE, but I don’t see a way to implement this in Agilex™ 5. Assuming I implement the alignment, skew compensation, and bit ordering correctly (use 10 instance GTS IP Core)— would this be a feasible way to receive a CAUI-10 stream? And if so — does it mean I could also implement CAUI-4 the same way (i.e. aggregating 4×25G manually), given that the transceivers can handle it individually?