Serial IO GPIO Host Controller - INT34BB
Hello, I would like to use the Intel GPIO controller in our applications that are written in .net. I have a motherboard with this controller, I have the pins wired out and I have the driver - but I cannot find any API or any information regarding how I can access this controller (or the pins) programmatically. Does anyone know where I can find a .net API, or any api or documentation for this? Thanks, Yanky
CYCLONE V - HPS and I2C Peripheral Pin
Hi Community I'm testing the I2C interface embedded in CycloneV - HPS. - However, if I export peripherals signals through the HPS I/O Set everything works pretty well. - But If I switch to FPGA: exporting signals to FPGA Fabric (integarting them with suitable I/O Tristate buffers) the I2C protocol is completely different, the frequency of I2C signals passes from 100kHx to 6 kHz, and even if SDA seems in a certain way coherent with data, SCL is not. Please note the different behavior in the images attached. Any help will be appreciated!
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Stratix 10 MCDMA host: Queue reset failed
Hello, I have been trying to get an MCDMA example design working on a Stratix 10 MX device (1SM21BEU2F55E2VG). You can consider me a beginner with the Intel FPGAs. The project details are as follows. Device side ----------------- Project: Platform designer project with H-tile PCIe MCDMA with AVMM interface. PCIe configuration - Gen3x16 512-bit interface, 250 MHz No of PFs - 1 Everything else is set to default, as this is a slightly modified version of the basic example design generated by Quartus. refclk - connected to differential PCIe clock PCIE_REFCLK_P and PCIE_REFCLK_N pin_perst - connected to PCIe PERST# npor - tied to 1 in the top level wrapper Verilog module xcvr - PCIe interface The top-level wrapper only instantiates this, sets npor to 1, and passes every other signals. The hip_ctrl and hip_pipe are left unconnected in the wrapper. The design compiles properly, and the sof file can be programmed without error. ----------------------- Host side ----------------------- On the host side, I followed the steps mentioned in the MCDMA example user guide. https://www.intel.com/content/www/us/en/docs/programmable/683517/23-4/introduction.html The device is listed the lspci output and shows up the BAR regions. However, when I try to run any of the test programs in the software/user/cli, nothing runs successfully (this driver and user utilities/examples are also generated as part of the example MCDMA project). Most of the time the error is "Queue reset failed" or the programs hang without any output. Reading device memory via the supplied devmem utility always returns 0xFFFFFFFF. My guess is something wrong with the reset logic/process, however I am unable to fix it so far and it feels like I am missing something obvious. Any lead in this regard would be helpful. Let me know if you need more information in this context. Thanks and regards, Arnab
Can't Connect to Display (arch linux on Stratix 10 w/ E9171 GPU)
Goal Connect Stratix10 to external display though embedded GPU via PICe, and run GlxGears. Problem: Though GPU is detected, can not connect to external display. Hardware Specifics Intel Stratix10 SoC H-Tile DevKit. Using the GHRD for FGPA image. Using AMD E-9171 GPU through on-board PCIe slot. OS Configuration Following instruction from Rocketboards (https://www.rocketboards.org/foswiki/Documentation/GSRDCompilingLinux_S10) we built the U-Boot and Linux Kernal as instructed, but then proceeded to use ARMv8 Generic Arch Linux RFS (https://archlinuxarm.org/platforms/armv8/generic). We chose this RFS as it has PacMan built in and made onboard development much easier. In this OS configuration used the xf86-video-amdgpu as our graphics driver. Details: To start we followed the bellow instructions to build out the Linux Kernal and U-Boot. https://www.rocketboards.org/foswiki/Documentation/GSRDCompilingLinux_S10 After multiple attempts we were able to get the Kernal and U-Boot to build, but never the actual File System. Because of this we chose to use the ARM ARCH Linux (below) Root File System, mainly because it has a package manager and I have used it extensively in the past. https://archlinuxarm.org Using PacMan (package manager) we installed all the necessary drivers and utils that should have the GPU up and running. We confirmed that the standard OpenAMD drivers will work, as we tested it on another system (x86). And doing this we can see that the GPU shows up with ‘lspci’. But when we run it with verbose printing ‘lspci -vvvvv’ we see that DevSta throws a CorrErr+ implying a correctable error. In addition to this we see that when running ‘dmsg’ the pcie slot for the GPU throws a lot of errors regarding the memory for the PCIe Bar Space allocation. See below that there is no space for the I/O on PCI Bar 4, this throws the error “[drm:radeon_device_init] *ERROR* Unable to find PCI I/O BAR” and fails the GPU initialization. [ 0.205970] OF: PCI: host bridge /soc/bridge@80000000/pcie@A0000000 ranges: [ 0.206012] OF: PCI: MEM 0x90000000..0x9fffffff -> 0x00000000 [ 0.206137] altera-pcie a0000000.pcie: PCI host bridge to bus 0000:00 [ 0.206154] pci_bus 0000:00: root bus resource [bus 00-ff] [ 0.206169] pci_bus 0000:00: root bus resource [mem 0x90000000-0x9fffffff] (bus address [0x00000000-0x0fffffff]) [ 0.206273] pci 0000:00:00.0: enabling Extended Tags [ 0.206490] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring [ 0.207310] pci 0000:01:00.0: enabling Extended Tags [ 0.208224] pci 0000:01:00.0: vgaarb: VGA device added: decodes=io+mem,owns=none,locks=none [ 0.208977] pci 0000:01:00.1: enabling Extended Tags [ 0.210459] pci 0000:01:00.2: enabling Extended Tags [ 0.211482] pci 0000:00:00.0: BAR 15: assigned [mem 0x90000000-0x97ffffff 64bit pref] [ 0.211500] pci 0000:00:00.0: BAR 14: assigned [mem 0x98000000-0x980fffff] [ 0.211514] pci 0000:00:00.0: BAR 13: no space for [io size 0x1000] [ 0.211527] pci 0000:00:00.0: BAR 13: failed to assign [io size 0x1000] [ 0.211545] pci 0000:01:00.0: BAR 0: assigned [mem 0x90000000-0x97ffffff 64bit pref] [ 0.211638] pci 0000:01:00.0: BAR 2: assigned [mem 0x98000000-0x9803ffff 64bit] [ 0.211728] pci 0000:01:00.0: BAR 6: assigned [mem 0x98040000-0x9805ffff pref] [ 0.211744] pci 0000:01:00.1: BAR 0: assigned [mem 0x98060000-0x98063fff 64bit] [ 0.211834] pci 0000:01:00.0: BAR 4: no space for [io size 0x0100] [ 0.211846] pci 0000:01:00.0: BAR 4: failed to assign [io size 0x0100] [ 0.211861] pci 0000:01:00.2: BAR 0: assigned [mem 0x98064000-0x9806407f 64bit] [ 0.211952] pci 0000:00:00.0: PCI bridge to [bus 01] [ 0.211968] pci 0000:00:00.0: bridge window [mem 0x98000000-0x980fffff] [ 0.211984] pci 0000:00:00.0: bridge window [mem 0x90000000-0x97ffffff 64bit pref] [ 0.212093] pcieport 0000:00:00.0: enabling device (0000 -> 0002) [ 0.212284] pcieport 0000:00:00.0: Signaling PME with IRQ 59 [ 0.212420] pcieport 0000:00:00.0: AER enabled with IRQ 59 [ 0.213420] EINJ: ACPI disabled. [ 0.218848] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled [ 0.220403] ffc02000.serial0: ttyS0 at MMIO 0xffc02000 (irq = 25, base_baud = 6250000) is a 16550A [ 1.278922] console [ttyS0] enabled [ 1.283095] SuperH (H)SCI(F) driver initialized [ 1.287881] msm_serial: driver initialized [ 1.292508] [drm] radeon kernel modesetting enabled. [ 1.297863] radeon 0000:01:00.0: enabling device (0000 -> 0002) [ 1.304149] [drm] initializing kernel modesetting (VERDE 0x1002:0x6822 0x0000:0x0000 0x00). [ 1.312504] [drm:radeon_device_init] *ERROR* Unable to find PCI I/O BAR [ 1.319221] radeon 0000:01:00.0: Invalid PCI ROM header signature: expecting 0xaa55, got 0x0000 [ 1.327959] radeon 0000:01:00.0: Invalid PCI ROM header signature: expecting 0xaa55, got 0x0000 [ 1.336669] [drm:radeon_get_bios] *ERROR* Unable to locate a BIOS ROM [ 1.343093] radeon 0000:01:00.0: Fatal error during GPU init This leads me to believe that it must be a Kernal/device tree issue, I am unsure how to proceed from here. Again, the goal is to get this system connected to an external display and run GlxGears. Hoping there is some simple step in setup I have overlooked, so any advice would be greatly apricated.Timing failure with external synchronous SRAM
I have a Cyclone V FPGA interfaced with an external synchronous (ZBT) SRAM. The FPGA is clocked with a 100 MHz XO, which is passed through the FPGA and forwarded/outputted to my SRAM as its clock. Obviously the FPGA has an address-bus connected (output) to the SRAM and a bidirectional data-bus from/to the SRAM. The relevant constraints I've used are: create_clock -name "clk_100_in" -period 10.000ns -waveform { 0.000 5.000 } [get_ports {clk_100_in}] create_generated_clock -name {sram_clk_out} -source [get_ports {clk_100_in}] [get_ports {sram_clk_out}] # SRAM input minimum delay in ns set_input_delay -clock sram_clk_out -min 1.3 [get_ports {sram_data36_inout*}] # SRAM input maximum delay in ns set_input_delay -clock sram_clk_out -max 3 [get_ports {sram_data36_inout*}] # SRAM output minimum delay (=hold time) in ns set_output_delay -clock sram_clk_out -min -0.5 [get_ports {sram_address21_out*}] set_output_delay -clock sram_clk_out -min -0.5 [get_ports {sram_data36_inout*}] # SRAM output maximum delay (=setup time) in ns set_output_delay -clock sram_clk_out -max 1.5 [get_ports {sram_address21_out*}] set_output_delay -clock sram_clk_out -max 1.5 [get_ports {sram_data36_inout*}] The problem is that I get consistent timing failures with the inputs for my SRAM->FPGA data-bus like this: When I report the timing for eg. data[31] I get: I think one of the issues I'm facing is the negative clock skew but I have no idea how to fix that. I've tried about a ton of things for several days now to get timing closure but I'm at a complete loss since I'm out of ideas. Any help would be greatly appreciated.
Input signal from other board measures an extra cycle wider on signaltap on Stratix 10 vs Cyclone 5
Hi, I am trying to interface the FTDI601 USB Bridge (https://ftdichip.com/products/ft601q-b/) to the Stratix 10 1SG10MHN3F74C2LG_U1/U2 FPGA on our design board. The reference clock for the interface is comes from the FTDI chip along with data/command signals. The signal RXF_N that indicates data coming from the FTDI chip appears one cycle wider when looked through signaltap on Stratix 10. The signal is asserted (active low) a cycle before the valid data. To verify that the software driving the FTDI chip and interface to FPGA is correct, We tested the example designs based on Cyclone V (https://ftdichip.com/wp-content/uploads/2024/08/cyclonev_mst_fifo32_1.2.zip) provided by FTDI (https://ftdichip.com/wp-content/uploads/2020/07/AN_421_FIFO_Bus_Master_For-FT60x.pdf). The design waveform as seen on signaltap is correct and the terminal data reading for the loopback design but for Stratix 10 has the RXF_N signal is wider (asserted one cycle earlier than data) For the working cyclone design the FTDI chip and the Cyclone V FPGA are on the same evaluation board (https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=165&No=830) and have a direct connection on board. For our design we have the FTDI board (https://ftdichip.com/products/umft601a-b/) with HSMC adapter connected to the Stratix 10 FPGA through an adapter board and connector on the FPGA. The image of the adapter is attached. I have attached signaltap image for both cyclone and Stratix. Please help figure what could cause the widening of RXF_N on Stratix device. The same loopback design and software is used on the same FTDI chip.
