Multirate IP FHT Support
Hello I am trying to create a reconfigurable FPGA device using FHT transceivers to generate the highest possible speed PAM4 outputs. I'd like to create a device that can switch between many speeds at the same time, however, the F-Tile PMA and FEC Direct PHY Multirate IP currently does not support FHTs being reconfigured in any way (neither does the dynamic reconfiguration IP). Is there any news about when this feature is to be added? Thanks
DAC Interface Instability After Migrating from MAX7000 to MAX10
Hi all, In one of our legacy designs, we used the MAX7000 (EPM7128AETC100-10N) CPLD. Due to obsolescence, we updated the design to use the MAX10 (10M04SCE144C8G). After the migration, we are observing instability in the DAC interface during operation. Has anyone encountered similar behavior when moving from MAX7000 to MAX10? Are there any known circuit-level differences, I/O characteristics, or design considerations we should account for to ensure stable DAC communication? If we made some correction on RC filter its working, reason is root cause is needed for implementation. Any guidance or insights would be greatly appreciated. Thanks Niranjan. D
Cyclone V Clamping Diode Electrical Specification
Hi, Please provide the below information for the Cyclone V Device IO Banks signals. what is the clamping voltage for the internal diode when enabled. what is the normal protection voltage for IO pin when clamping diode is not enabled. What is the diode used for an Clamping diode, is it an Zenor Diode or TVS Diode or Schottky Diode
Internal LVDS loopback in Agilex I/O tile
Hi, I’m trying to figure out if it’s possible on Agilex 5 to connect an internal output buffer to the true-differential LVDS input buffer inside the same I/O tile to create an internal loopback without routing through the package pins. The goal is to replicate the kind of setup used in this paper, where an output driver feeds a differential input (comparator) entirely inside the FPGA to build an ADC. This was done on an Xilinx Ultrascale+, while I'd like to do it on an Agilex 5. I’ve tried using the GPIO and LVDS SERDES IPs, but both seem to route only to the pads. Is there any way in Quartus Prime Pro or with the Agilex GPIO/SERDES IPs to tie an output buffer directly to the differential input buffer internally, or is this physically impossible on Agilex 5? Thanks!
Agilex 5 mixed TX-RX in one lane
Hello It's unclear for me about how to use IO LANE with SERDES functionality. Is this mean that one LANE can only work as TX or RX block in SERDES mode? If yes, if whole one LANE is set to (for example) TX, still I can put there RX diff pair without SERDES or single ended IO pin?
Agilex 7 I-Series Dev Kit: PIPE Direct for custom PCIe/CXL controller?
Hi Intel Community, I’m studying the R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide and considering purchase of the Agilex™ 7 FPGA I-Series Development Kit (2× R-Tile, 1× F-Tile). My research goal is to bypass the hardened PCIe/CXL controller and expose the PIPE 5.x SerDes interface into the FPGA fabric, so that I can run a custom soft controller (own LTSSM, EQ, DLLP/TLP, later extend to CXL.io → CXL.mem with 64B FLITs). Before purchasing, I’d like to confirm: PIPE Direct availability Does the I-Series Dev Kit expose R-Tile PIPE Direct to the fabric (via EMIB), enabling a full soft PCIe/CXL controller? Any board-level constraints (e.g., octet-wide Gen5 base mode, per-lane Rate2:0/Powerdown1:0 controls)? Tool/flow support The User Guide notes that Quartus Pro 21.2 had no example/testbench for PIPE Direct. What is the current Quartus Pro version recommended? Are there any reference stubs or app notes for PIPE Direct (Tx/Rx wrapper, reset/clocking examples)? Root Port / Endpoint configs Any guidance on PERST#, equalization sequencing, retrain, refclk selection when not using the hardened controller? CXL hybrid approach If I start with CXL.io only, is it possible to use the hardened PCIe IP just for link/LTSSM while running custom DLL/TLP/CXL layers in soft logic? Or does any custom higher-layer implementation require going fully PIPE Direct? Board I/O Which ports (x16 edge connector, MCIO/SFF-TA-1016) are usable in PIPE Direct mode? Any pinout or kit-specific notes? specifically: if I connect through the edge connector (to a host system), can I still operate the R-Tile in PIPE Direct mode with my soft controller, or is PIPE Direct limited to MCIO breakout only? Validation environment (important) I have access to a CXL-capable host (Sapphire Rapids) but no PCIe/CXL protocol analyzer. Is it realistic to debug link training and equalization in PIPE Direct without an analyzer? If yes, what tools/flows are recommended (ILA debug, Quartus monitors, logging)? Would you recommend starting with two Agilex kits back-to-back instead of host-only, given that I don’t have an analyzer? Are there any Intel or third-party reference setups for early CXL bring-up without protocol analyzers? I’d greatly appreciate any application notes, example projects, TCL scripts, or checklists to help with PIPE Direct bring-up. Thanks in advance!Unexpected Voltage output on pin AB19
For this pin (AB19) we are seeing partial transition from 1.8 V to 1.3 V. The good PCBA the upper level is 1.8 volt rail. On a good PCBA, the lower level is ≤ 0.3 V. On a bad PCB, the upper level is 1.8 volt rail. On a good PCBA, the lower level is ≤ 1.3 V. This level does not allow the remainder of the circuit to detect the lower level transition.CAUI‑4 reception on Agilex 5 via GTS PHY IP?
Hello, Does Agilex 5 support CAUI‑4 input for implementing a 100G Ethernet receive path? I’m working on a design where I intend to receive 100G Ethernet from a QSFP28 module, using 4 lanes at 25.78125 Gbps. According to Intel documentation, Agilex 5 transceivers support: up to 28.9 Gbps NRZ, standard PCS (64b/66b), and interfaces like XLPPI, XLAUI, etc. However, CAUI‑4 is not explicitly mentioned in Agilex 5 documentation or IP catalog, while previous devices like Arria 10 do mention it directly. I configured the GTS PMA/FEC Direct PHY IP with 4 × 25.78125 Gbps and enabled PCS (IEEE MII / PCS66). The IP compiles successfully in Quartus Pro 25.1, and simulation passes. But it’s unclear whether this configuration is officially supported, or sufficient to receive and deserialize CAUI‑4 input from QSFP28. Also, I encountered conflicting documentation: One source says PCS is not supported above 17.16 Gbps. Another states that "Ethernet mode: 4 × 10/25 GbE PCS direct mode (64b/66b hard IP)" is supported. Here are my questions: Can we implement CAUI‑4 reception manually using GTS PHY IP with PCS enabled? Is there a soft MAC IP (even licensed) available that supports this 100G aggregation for Agilex 5? Are there any Quartus 25.1 limitations for this mode we should be aware of? Thank you in advance!
