LVDS SERDES rx_inclock idle
Hi, We are using LVDS SERDES IP as a multichannel LVDS receiver in Cyclone 10 GX device. The reciver is configured to run at DDR mode using 200MHz rx_inclock. The transmitter device output clock is not a free-running clock and is subjected to changes with correlation to the output data (for example clock is only running when the transmitter outputs data). I see in the Altera LVDS SERDES IP Core User Guide that the SERDES use IO PLL for that clock, meaning it should meet IO PLL cycle-to cycle clock jitter for the PLL input. Does that means that only a free running clock at a constant frequency and duty cycle can be used as part of the LVDS bus? How should i treat devices that has an LVDS bus clock that is correlated with data?
[CycloneV SX] LVDS IO datarate
Hi, I am trying to interface a Cyclone V SX (DE10 standard) with a 500MSPs DAC (AD9783). The DAC uses 17 x LVDS DDR parallel inputs. The double datarate is used by the DAC to take 2x So I set up the FPGA outputs to LVDS standard (2.5V), and using the alt_ddio megafunction. The timing constraints for the clock is set to 500MHz. However, the timing analyzer tells me that the maximum achievable datarate is 275MHz. From what I have gathered here, the FPGA should be able to sustain a datarate of 640Mbps only using the softcore. My simple question is : Is the LVDS maximum datarate only achievable when using the LVDS Softcore? Thank you for your answer.
Multirate IP FHT Support
Hello I am trying to create a reconfigurable FPGA device using FHT transceivers to generate the highest possible speed PAM4 outputs. I'd like to create a device that can switch between many speeds at the same time, however, the F-Tile PMA and FEC Direct PHY Multirate IP currently does not support FHTs being reconfigured in any way (neither does the dynamic reconfiguration IP). Is there any news about when this feature is to be added? Thanks
DAC Interface Instability After Migrating from MAX7000 to MAX10
Hi all, In one of our legacy designs, we used the MAX7000 (EPM7128AETC100-10N) CPLD. Due to obsolescence, we updated the design to use the MAX10 (10M04SCE144C8G). After the migration, we are observing instability in the DAC interface during operation. Has anyone encountered similar behavior when moving from MAX7000 to MAX10? Are there any known circuit-level differences, I/O characteristics, or design considerations we should account for to ensure stable DAC communication? If we made some correction on RC filter its working, reason is root cause is needed for implementation. Any guidance or insights would be greatly appreciated. Thanks Niranjan. D
Cyclone V Clamping Diode Electrical Specification
Hi, Please provide the below information for the Cyclone V Device IO Banks signals. what is the clamping voltage for the internal diode when enabled. what is the normal protection voltage for IO pin when clamping diode is not enabled. What is the diode used for an Clamping diode, is it an Zenor Diode or TVS Diode or Schottky Diode
Internal LVDS loopback in Agilex I/O tile
Hi, I’m trying to figure out if it’s possible on Agilex 5 to connect an internal output buffer to the true-differential LVDS input buffer inside the same I/O tile to create an internal loopback without routing through the package pins. The goal is to replicate the kind of setup used in this paper, where an output driver feeds a differential input (comparator) entirely inside the FPGA to build an ADC. This was done on an Xilinx Ultrascale+, while I'd like to do it on an Agilex 5. I’ve tried using the GPIO and LVDS SERDES IPs, but both seem to route only to the pads. Is there any way in Quartus Prime Pro or with the Agilex GPIO/SERDES IPs to tie an output buffer directly to the differential input buffer internally, or is this physically impossible on Agilex 5? Thanks!
Agilex 5 mixed TX-RX in one lane
Hello It's unclear for me about how to use IO LANE with SERDES functionality. Is this mean that one LANE can only work as TX or RX block in SERDES mode? If yes, if whole one LANE is set to (for example) TX, still I can put there RX diff pair without SERDES or single ended IO pin?
