Will serialization factor of 6 in LVDS serdes IP be supported in the future on Agilex5?
I was hoping to use LVDS serdes IP to implement acquisition system of 12 -bit ADC data using 2-wire LVDS: However, this is not possible if only serialization factors of 4 and 8 are supported. Is there a workaround or will this be supported in the future?
Request for Cyclone V Pinout File Information
I would like to download the Cyclone V pinout file (Excel format) from the Altera website; however, an error occurs and I am unable to download the file. https://www.altera.com/design/devices/resources/pinouts Could you please advise on how to resolve this issue and inform me of any alternative methods to obtain the Cyclone V pinout file?
Question for LPDDR5 power sharing guideline
Hi altera, In the Agilex 7 M-series Pin connection guideline document, I can find guidline for Agilex™ 7 M-Series Devices with R-Tile and F-Tile, Without HBM2E Using LPDDR5. 1.7.2. Example 2— Agilex™ 7 M-Series Devices with R-Tile, F-Tile and HBM2E Using DDR5 • Agilex™ 7 Device Family Pin Connection Guidelines M-Series • Altera Documentation and Resources Center When applying LPDDR5 component to the Agilex 7 M-series, which section should I refer to regarding the power sharing guideline? Thanks.Does the Agilex7 M-series support LPDDR5X component?
Hi Altera, I want to use a LPDDR5X component on Agilex 7 M-series. Does the Agilex7 M-series support LPDDR5X components? The LPDDR5X part number is MT62F1G32D2DS-020 WT:D Functional Technology Supply Voltage Useable Density Configuration Width Data Rate Clock Speed MT62F1G32D2DS-020 WT:D LPDDR5X 1.05 VOLTS 32Gb X32 9600MTPS 4800 Thanks.
Bidirectional differential port on MAX10
I want to implement a bidirectional differential port on a MAX10 10M02SCU324C8G I first tried to do it on my own and then tried to do it with the GPIO Lite IP too. At the end of the day I get the same error: Error (176202): The differential I/O standard Differential 2.5-V SSTL Class I cannot be used on the pin RC_A[0], because the specified pin uses a tri-stated output buffer. Is it only possible to have either a dedicated input or output differential port? Why is it even letting me configure the IP as a bidirectional differential IO? Or am I missing something when it comes to pin configuration?
Agilex 7 F/I Series True Differential Input Termination
Hi, The Agilex F/I Series GPIO User Guide indicates that if using AC coupling for the true differential inputs you should add external voltage bias circuitry and has no examples of AC coupling without also externally biasing the inputs as shown in snippet below. I would like to confirm whether the Agilex 7 F/I series parts have internal voltage biasing such that if AC coupling, external biasing resistors would not be needed so long as VID (max 600mV, so 1200mV differential pk-pk max) is being met? The IBIS model for the part shows a consistent voltage bias for the inputs that is within the VICM range listed in the Agilex 7 F/I series datasheet (see snippet below) which implies the external biasing is not needed. And the AGILEX FM86/FM76 DEVELOPMENT KIT has some differential inputs that are AC coupled with no external biasing.Agilex 7 F Series Transceiver Pins Allowed Voltages During Powerup/When Unpowered
Hello, I would like to confirm the voltages allowed on the Agilex 7 F series Transceiver I/O (the Transceiver Data lanes and the REF_CLK inputs) during power-up or when the Agilex and its transceivers tiles are not powered. For example, I'd like to know if a scenario where Agilex interfaces to an external PCIe host that may drive PCIe clock to the Agilex Transceiver REF_CLK input before it's powered/while it's powering up is acceptable. The requirements for the Agilex GPIO, HPS_IO, and SDM_IO during powerup/when unpowered are clear to me from below documents but not the Transceiver I/O. I don't see any constraints specified for the Transceiver I/O during powerup unless I'm missing it. Can you please confirm this for me, or point me to where this is documented? If it matters, I am interested specifically in F-tile. The A692 Power Sequencing Considerations app note states the below: So it's clear for Cyclone GX, Arria 10, and Stratix 10 L/H tiles that no activity is allowed (with exception of 1.0 Vp-p on Stratix 10) on transceiver I/O during power-up but Agilex is not mentioned in this section. The Agilex 7 General-Purpose I/O User Guide states the following: Table 3: GPIO pin voltage must not exceed VCCIO_PIO or 1.2V, whichever is lower Table 22: HPS I/O pin voltage must not exceed VCCIO_HPS. Table 29: SDM I/O pin voltage must not exceed VCCIO_SDM. I don't see any mention of similar constraint for Transceiver I/O. The Agilex 7 Power Management User Guide states the following: Again, I see all I/O other than Transceiver I/O mentioned. Thanks!1.8 V LVDS Receiver Timing Specifications for Intel MAX 10 Dual Supply Devices
Hi all! I need to receive data from ADC to MAX10 device in my project. The issue is that data rate is 500 Mbps and input clock frequency is 250 MHz. I checked Intel® MAX® 10 FPGA Device Datasheet and found in table 48 that maximum supported frequency is 200 MHz. BUT according to the text in brackets this information is regarding bottom-bank I/O performance pin (I do not exactly understand what it means). I wonder if there is a way to receive 1.8 V LVDS signal on 250 MHz frequency (maybe using other I/O banks). And what should be pin assignment settings for that? Speed grade is 7, dual supply, FBGA256 package. Thanks, ValentynQSPI DDR Interface with Cyclone10LP: Maximum frequency
Hello, We are planning to implement a QSPI interface between Altera Cyclone10LP (10CL025YU256A7G) and a microcontroller iMXRT1180. The microcontroller is capable of a maximum frequency of 166 MHz (which would mean 332MHz DDR) on the QSPI interface. We want to know which would be the maximum frequency we are able to achieve on the FPGA for this interface. We have this information extracted from the datasheet: "I/Os using general-purpose I/O standards such as 3.3-, 3.0-, 2.5-, 1.8-, or 1.5-LVTTL/LVCMOS are capable of a typical 200 MHz interfacing frequency with a 10 pF load." Does this mean the pins will not be able to accept data changing at a rate faster than 200 MHz or will it be possible to have something like a fHSCLK of 200 MHz (which would mean double device operation in Mbps) as we can see in Table 24 (example for RSDS Transmitter) on the datasheet? Are there any special pins on the FPGA which we can use to achieve maximum potential on this interface? Or any strategies like using IDDR/ODDR modules that could help? Any suggestions are welcome. Thank you!
