Shift Register triggers occassionally on both clock edges
Good morning community, in my project a MAX10 M08 FPGA serves as an interface between a microcontroller and an ADC board with 32 channels. In order to parallelize the serial data from the board I developed a shift register. This register shall only read the first 512 bits of a data stream. Therefore a counter is included. -- serial-parallel converter synchronous to falling edge of DCLK p_ser_par_dclk : process (DCLK,nRES) is begin if (nRES = '0') then dout0_shr_dclk <= (others => '0'); dout1_shr_dclk <= (others => '0'); mod1023_count_i <= 0; elsif (falling_edge(DCLK)) then -- resets counter when nDRDY active if (nDRDY = '1') then mod1023_count_i <= 0; elsif (mod1023_count_i < 512) then mod1023_count_i <= mod1023_count_i + 1; end if; -- counter masks the 512 DCLK clock edges without data if (mod1023_count_i < 512) then -- shift-registers, alert bit, address bits, CRC bits shifted, maybe later omitted dout0_shr_dclk(0) <= DOUT0; dout1_shr_dclk(0) <= DOUT1; dout0_shr_dclk((snr_length - 1) downto 1) <= dout0_shr_dclk((snr_length - 2) downto 0); dout1_shr_dclk((snr_length - 1) downto 1) <= dout1_shr_dclk((snr_length - 2) downto 0); -- no shifting else dout1_shr_dclk <= dout1_shr_dclk; dout0_shr_dclk <= dout0_shr_dclk; end if; end if; end process p_ser_par_dclk; The data from the AD converters contains the channel number. Therefore there must be regular data patterns in the 512 bit wide vector when a complete set of 16*32bit have been written into the FIFO. I could never see this pattern when I visualized the internal data with the signal tap analyzer. What I can occassionally see is that the shift registers and the counter triggers at the wrong edge. This is a severe error. What could be the reason? Best regards Christof Abt
Timing Behavior of Remote Update IP After Reset on Cyclone 10 GX (10CX150YF672E5G)
I am using the Remote Update IP with the Cyclone 10 GX FPGA, part number 10CX150YF672E5G. I observed that the Remote Update IP does not respond properly after reset until approximately 300 µs. I experimented with delays of 1 µs and 2 µs after reset, but did not observe the expected behavior. However, after waiting for 300 µs, the IP responded as expected. Previously, I used the same Remote Update IP with a different part number, 10CX150YF672I5G, and in that case, it worked as expected with just a 10 clock cycle delay after reset. Could you please confirm if there is a specific timing requirement after reset for initializing the Remote Update IP with the 10CX150YF672E5G device? I am using Quartus Prime Pro 24.2 tool for Both version of Cyclone 10GX FPGA(10CX150YF672E5G & 10CX105YF672I5G) Thank you.
DAC Interface Instability After Migrating from MAX7000 to MAX10
Hi all, In one of our legacy designs, we used the MAX7000 (EPM7128AETC100-10N) CPLD. Due to obsolescence, we updated the design to use the MAX10 (10M04SCE144C8G). After the migration, we are observing instability in the DAC interface during operation. Has anyone encountered similar behavior when moving from MAX7000 to MAX10? Are there any known circuit-level differences, I/O characteristics, or design considerations we should account for to ensure stable DAC communication? If we made some correction on RC filter its working, reason is root cause is needed for implementation. Any guidance or insights would be greatly appreciated. Thanks Niranjan. DSignal Tap false trigger
I'm using Quartus Signal Tap to capture waveforms and encountering a false triggering issue (triggering when the trigger condition is not met, for example, trying to capture the moment when a signal that is constantly low becomes high, but it captures incorrectly). When this false trigger occurs, only half of the waveform is displayed (only the waveform after the trigger position). Has anyone experienced a similar problem? How can this be resolved? (Agilex 7 using HPS)
Cyclone V 2.5V LVPECL vs LVDS inputs
When feeding an AC coupled LVPECL differential signal into a Cyclone V FPGA, the Cyclone V datasheet appears to indicate that DC bias and OCT 100 ohm differential termination is not available when Assignment editor specifies differential I/O as LVPECL. Furthermore, LVPECL inputs are limited to CLK input pins. Questions: 1. Are my comments above correct? 2. Per Cyclone V datasheet LVDS I/Os appear to be able to receive an AC coupled LVPECL signal which would enable internal chip provided DC biasing and OCT 100 ohms by simple Assigning LVPECL input to LVDS in Assignment editor. Is this true? Are there any negatives? Thank you in advance, Tony
