Server rehosting new license file not matching current license file tools.
Our company decided to provide new on the cloud servers. As I try to migrate to new server, I added it to Intel database and generated new license file. Unfortunately, new license file is missing Quartus tools. Please refer to attachments.
Platform designer very slow when opening top level system (21.1 Std)
Hello, I am currently working on a FPGA project with the Quartus Prime Standard 21.1 software. When opening the top level QSYS-file it takes forever to finally finish (multiple hours). I have tested it with the same design on multiple machines including: - i7 8700K with 32GB RAM and corporate Windows 10 OS - i9 12900K with 64 GB and corporate Windows 10 OS - i5 7500 with 8 GB RAM and standard Windows 10 OS (to make sure it wasn't the corporate Windows 10 OS) The different hardware didn't seem to make a difference when opening the top level. When opening a subsystem that is instantiated in the top level the Platform Designer doesn't take nearly as long. All of them open within 1 minute and one -taht includes most of the logic - takes about 20minutes to open. When building the whole FPGA it takes 5.5h on the i7 8700K and 3h on the i9 12900K machine. Most of the time is spent in Analysis&Synthesis: the i7 takes about 4h and the i9 2.5h here. I assume that this is caused by the same problem that causes the top level file to be opened so slowly. I have worked on multiple designs with this version of Quartus but have never encountered a similar issue. The project I am currently working on consumes ~80% of the ALM and ~35% of the memory bits in the Arria 10 GX with 270kLE. Unfortunately I cannot share the files themselves due to corporate regulations. Are there any known issues with certain system design choices that can cause the platform designer/quartus to perform so poorly when opening or processing Analysis&Synthesis? Best Regards, Florian
Not able to do fitting design with Quartus 22.1
Hi, I am able to fit the attached design with Version 22.1std.0 Build 915 10/25/2022 SC Standard Edition. However, I can fit the design with ease in Version 19.1.0 Build 670 09/22/2019 SJ Standard Edition Please suggest what changes required to in settings file. Attached qsf file (extension changed to .txt to attach here) and report files both versions. The error I got with Version 22.1std.0 Build 915 10/25/2022 SC Standard Edition is "Error (170011): Design contains 249203 blocks of type combinational node. However, the device contains only 227120 blocks." Please note, due to confidentiality, I can't make available the source codes for these builds. Regards, Vikram
Preservation level: Final leads to Quartus crash on re-run
Preservation level: Final leads to Quartus crash on re-run. Quartus does not crash when I use the synthesize preserve level (or no preserve). Crash log + picture after the crash message (closed). No pin location warning is expected, this is just a trial to test the partition flow/resources usage. Problem Details Error: Internal Error: Sub-system: PCC, File: /quartus/periph/pcc/pcc_port_rotation_util.cpp, Line: 1672 old_physical == logical Stack Trace: Quartus 0x61fdc: PCC_PORT_ROTATION_UTIL_ITERMS::apply_a2c_directives(CDB_ATOM_NODE*, std::vector<std::pair<DB_INPUT_PORT_TYPE, unsigned short>, std::allocator<std::pair<DB_INPUT_PORT_TYPE, unsigned short> > > const&, std::vector<std::pair<DB_INPUT_PORT_TYPE, unsigned short>, std::allocator<std::pair<DB_INPUT_PORT_TYPE, unsigned short> > > const&) + 0x380 (periph_pcc) Quartus 0x5c605: PCC_PORT_ROTATION_UTIL_ITERMS::process_routing(bool*) [clone .cold] + 0x3b1 (periph_pcc) Quartus 0x3d3eb: CPLL_GEN6::rotate_iterms() + 0x3b (periph_cpll) Quartus 0x50019: CPLL_GEN7::post_process_legal_placement() + 0x59 (periph_cpll) Quartus 0xc0818: PCC_ENV_IMPL::perform_op(PCC_ENV::OP) + 0x1b8 (periph_pcc) Quartus 0xc209f: PCC_ENV_IMPL::refresh_placement_until_converged() + 0x16f (periph_pcc) Quartus 0xc1ea7: PCC_ENV_IMPL::commit() + 0x47 (periph_pcc) Quartus 0xf7f70: PCC_PERIPH_FLOW::plan() + 0x210 (periph_pcc) Quartus 0x39d1b: fit2_fit_plan + 0x7c9 (comp_fit2) Quartus 0x50fb7: TclNRRunCallbacks + 0x47 (tcl8.6) Quartus 0x527df: TclEvalEx + 0x94f (tcl8.6) Quartus 0xfa3a6: Tcl_FSEvalFileEx + 0x266 (tcl8.6) Quartus 0xfa4be: Tcl_EvalFile + 0x2e (tcl8.6) Quartus 0x2a8fc: qexe_evaluate_tcl_script(std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&) + 0x3de (comp_qexe) Quartus 0x2dd73: qexe_do_tcl(QEXE_FRAMEWORK*, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&, std::__cxx11::list<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >, std::allocator<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > > > const&, bool, bool) + 0x4c2 (comp_qexe) Quartus 0x2ee7b: qexe_run_tcl_option(QEXE_FRAMEWORK*, char const*, std::__cxx11::list<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >, std::allocator<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > > >*, bool) + 0x66e (comp_qexe) Quartus 0x6d1ec: QCU::DETAIL::intialise_qhd_and_run_qexe(QCU_FRAMEWORK&, FIO_PATH const&, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&, char const*, std::__cxx11::list<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >, std::allocator<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > > >*, bool) + 0x9c (comp_qcu) Quartus 0x6d638: qcu_run_tcl_option(QCU_FRAMEWORK*, char const*, std::__cxx11::list<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >, std::allocator<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > > >*, bool) + 0x343 (comp_qcu) Quartus 0x3421d: qexe_standard_main(QEXE_FRAMEWORK*, QEXE_OPTION_DEFINITION const**, int, char const**) + 0xba2 (comp_qexe) Quartus 0x40ad6c: qfit2_main(int, char const**) + 0x8c (quartus_fit) Quartus 0x4e546: msg_main_thread(void*) + 0x10 (ccl_msg) Quartus 0x4f764: msg_thread_wrapper(void* (*)(void*), void*) + 0x8c (ccl_msg) Quartus 0x1f568: mem_thread_wrapper(void* (*)(void*), void*) + 0x98 (ccl_mem) Quartus 0x10f3a: err_thread_wrapper(void* (*)(void*), void*) + 0x1e (ccl_err) Quartus 0xb7f5: thr_thread_wrapper + 0x15 (ccl_thr) Quartus 0x4f684: msg_exe_main(int, char const**, int (*)(int, char const**)) + 0xd8 (ccl_msg) System 0x22555: __libc_start_main + 0xf5 (c) Quartus 0x4062a9: _start + 0x29 (quartus_fit) End-trace Executable: quartus Comment: None System Information Platform: linux64 OS name: Red Hat OS version: 7 Quartus Prime Information Address bits: 64 Version: 22.4.0 Build: 94 Edition: Pro Edition
Signals(nodes) in Signal Tap Node Window Disappear
All of a sudden, the signals in in the Signal Window started disappearing whenever I change the view from "Data" to "Setup" or vica versa. I can get them to reappear by going down tothe "Hierarchy Display" window a clicking the box for the module that the signals are from. For example, if I have selected signals from and module called "mono_out", there is a "mono_out" entry in the "Hierarchy Display" window with a check box next to it. If this box is checked the signals from the "mono_out" module show up in the Signal Window. This box now always gets unchecked when I switch between "Data" and "Setup" and the corresponding signals disappear in the Signal Window. This did not happen until today when I switched to Quartus Prime Version 22.1std.2. How do I stop this from happening?
HAL Kernel Version Mismatch Error During FPGA Emulation with vector-add Sample
Hello Intel FPGA team, I'm currently working on the vector-add example from the official oneAPI-samples repository, specifically from: DirectProgramming/DPC++/DenseLinearAlgebra/vector-add I’m encountering the following runtime error when I attempt to run the emulation build: Error output: ./vector-add-buffers.fpga_emu HAL Kern: Version mismatch! Expected 0xa0c00001 but read 0x4130 Hardware version ID differs from version expected by software. Either: a) Ensure your compiled design was generated by the same ACL build currently in use, OR b) The host can not communicate with the compiled kernel. vector-add-buffers.fpga_emu: /nfs/sc/disks/swip_hld_1/ops/SC/hld/nightly/2022.1/96.2/l64/work/acl/acl/source/57c9d2bcb46afcf445b5da2406c0e6d85be93ef3/src/acl_kernel_if.cpp:733: int acl_kernel_if_init(acl_kernel_if*, acl_bsp_io, acl_system_def_t*): Assertion `0' failed. make: *** [Makefile.fpga:35: run_emu] Error 1 Environment details: Board: DE10-Agilex BSP Path: /opt/intel/oneapi/intelfpgadpcpp/2021.4.0/board/de10_agilex oneAPI version: Installed multiple versions. Active: 2022.0.2 dpcpp path: /opt/intel/oneapi/compiler/2022.0.2/linux/bin/dpcpp OS: Ubuntu (detected as Rocky Linux during install attempts) What I have tried: Verified the AOCL_BOARD_PACKAGE_ROOT is correctly set. Recompiled the design using make clean && make fpga_emu. Ran aoc -list-board-packages to confirm the installed board. Ensured Quartus, BSP, and compiler are aligned. Despite that, I still encounter the HAL version mismatch. Request: Could someone guide me on how to: Resolve this version mismatch issue? Confirm the correct environment and runtime versions are in sync? Completely clean older/duplicate oneAPI installations if that’s the root cause? @intel @OneAPI @fpga @agilex7 @de10 @intel6
