Why does the maximum observed channel-to-channel skew exceed 2 UI + 125 ps in an E-Tile transceiver under NRZ mode, even when TX PMA bonding is enabled?
Description Due to a problem in the Quartus® Prime Pro Edition software version 25.3.1 and earlier, you may observe channel-to-channel skew exceeds 2 UI + 125 ps in E-Tile transceivers under NRZ mode even when TX PMA bonding is enabled. Resolution There is no workaround currently, and there is no plan to fix this problem.Why are there PCIe* functional failures observed after a Configuration via Protocol (CvP) update in Agilex® 7 FPGA devices (R-Tile) CvP designs?
Description Due to a problem in Quartus® Prime Pro Edition software versions 25.3.1 and earlier, when using Configuration via Protocol (CvP) for Agilex® 7 FPGA devices (R-Tile), you may observe PCIe* functional failures after performing a CvP update, as the PCIe interface becomes non-functional. During the CvP update, the FPGA fabric is reconfigured and held in reset, while the PCIe Hard IP is not reset. This issue occurs because the R-Tile RTL is unable to handle the handshaking between the PCIe Hard IP and the fabric after the CvP update. Note that this issue does not cause the PCIe link to go down. This issue affects designs using R-Tile with both CvP and PCIe. Designs using R-Tile without CvP are not affected. This issue occurs in the following flow: CvP Periphery image CvP Initialization CvP Update PCIe activity Issue observed The following sequences will not trigger the problem: A CvP update without PCIe activity after CvP Initialization PCIe activity without a CvP Update after CvP Initialization Resolution To work around this problem, reconfigure the FPGA. Note that this fix may introduce a few seconds of additional delay during the CvP update in the teardown process. This delay occurs after the core.rbf file is transferred during every CvP update. During teardown, the CvP driver polls the CVP_CONFIG_READY bit in the CvP Status Register until CVP_CONFIG_READY equals 0, which accounts for the additional delay. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. Related IP R-Tile Avalon Streaming IP for PCI Express Multi Channel DMA IP for PCI Express AXI Streaming IP for PCI ExpressWhy is the power estimation of HPS core power rails inaccurate?
Description Due to a problem in the Power & Thermal Analyzer and Quartus Power Analyzer version 25.3.1 and earlier, the power estimation of HPS core power rails (VCCL_HPS, VCCL_HPS_CORE0_CORE1, VCCL_HPS_CORE2 and VCCL_HPS_CORE3) for Agilex® 3, Agilex® 5 and Agilex® 7 FPGA devices might be inaccurate if the CPU frequency field in PTA is empty or contains the wrong frequency. Resolution To work around this problem, manually import existing PTC/PTA/QPTC/QPTA files into the Power & Thermal Analyzer and ensure the CPU frequency field is filled with the correct frequency value: For Agilex 7 FPGA devices, ensure the CPU frequency field contains the highest CPU frequency used in your design For Agilex 3 and Agilex 5 FPGA devices, ensure the CPU frequency field contains the DSU frequency of your design. The DSU frequency is the highest CPU frequency (A55/A76 core frequency) used in your design divided by 1.5 This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software.Why does the HPS boot up delay after trigger HPS cold reset via the external reset pin?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.2, when the multi-flash support feature is introduced, the flash recovery flow tries to recover the flash by re-attempting the calibration step before resetting the flash. This recovery approach causes the flash recovery flow to fail, then triggers the watchdog timer. Resolution The fix is to remove the re-calibration step and reset the flash device during the flash recovery flow. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.Why does Vendor Authorized Boot (VAB) certificate authentication failed in SDM?
Description During the Second-Stage Bootloader (SSBL), you may encounter an intermittent timeout while transferring the initial 32‑word block of the VAB certificate command Error message displayed: #ret = 0x000007ff, resp = 0x00000000, resp_len = 1 #VAB certificate authentication failed in SDM #### ERROR ### Please RESET the board ### Resolution To avoid this problem, upgrade the socfpga_v2.12.1 (socfpga_mailbox.c) An ATF patch for socfpga_v2.12.1 is available to fix this problem : Download and install patch mbox.patch from the attachment below. This problem is scheduled to be resolved in a future ATF releasedWhy does the FCS‑client abort during provision‑data retrieval when the number of owner‑root‑hash slots is changed to 5?
Description After provisioning 5 owner root hash, FCS client aborts during get provision data command command for fcs-client on get provision data (read efuse) : ./fcs_client –G <name>.bin -p --loglevel=4 Error message displayed when perform command fcs-client on get provision data on 5 owner root hash: root@agilex:~# fcs_client -G a.bin -p --loglevel=4 [dbg:]Retrieving provision data [dbg:]sysfs attribute /sys/kernel/fcs_sysfs/prov_data munmap_chunk(): invalid pointer Aborted perform owner root hash cancellation for root2,root3, and root4, get provision data command from FCS-client still remain “0”. command for fcs-client cancel owner root : ./fcs_client –c <name>.ccert –c <volatile = 1 / non-volatile =0> Error message displayed when perform command fcs-client on get provision data on 5 owner root after perform owner root hash cancellation for root2,root3 and root4: root@agilex :~# fcs_client -C signed_root4_cancel.ccert -c 1 root@agilex :~# fcs_client -C signed_root3_cancel.ccert -c 1 root@agilex :~# fcs_client -C signed_root2_cancel.ccert -c 1 root@agilex :~# fcs_client -G a.bin -p W0:Provision Status Code: 0x0 W1:Key Cancellation Status: 0x7F W2:Co-Sign Status: 0 W2:RootHash0 Cancel Status: 0 W2:RootHash1 Cancel Status: 0 W2:RootHash2 Cancel Status: 4 W2:RootHash3 Cancel Status: 0 W2:RootHash4 Cancel Status: 0 W2:Number of Hashes: 5 W2:Type of Hash: secp384r1 Resolution To avoid this problem, upgrade the libfcs with install the following patch: fix_read_provision_5_root_hash_v2.patch This problem is scheduled to be resolved in a future release of the libfcs.Why did the FCS client fail to verify the Vendor Authorized Boot (VAB) file?
Description You might see this error when performing a VAB file verification via fcs_client (e.g., signed-bl31.bin , u-boot.itb, kernel.itb). command for read out session ID: ./fcs_client -e command for perform verification : ./fcs_client –V <bitstream.vab> -s <sessionID> --loglevel=4 Error message display, when verified signed-bl31.bin: root@agilex7dksiagf014eb:~# ./fcs_client -V signed-bl31.bin -s 869f2929-c2d3-b64a-bbc7-c003718d60ed --loglevel=4 [ 2831.587900] Session UUID Mismatch ret: -22 [ 2831.592065] Failed to initialize digest ret: -22 [ 2831.596698] Failed to perform get digest update [err:]Failed to write to sysfs attribute [err:]Error in getting digest [err:]Error in calculating image hash [err:]Error in verifying image hash noffset=0 Error message display, when verified u-boot.itb/kernel.itb: root@agilex7dksiagf014eb:~# ./fcs_client -V u-boot.itb-s 869f2929-c2d3-b64a-bbc7-c003718d60ed --loglevel=4 [err:]Error in getting image data noffset = Resolution To solve this problem, you will need install the patch for libfcs: fix-image-validation-issues3.patch This problem is scheduled to be resolved in a future release of the libfcs.How can I tell if a Raw Binary File (.rbf) is a PR Bitstream File?
Description A customer can tell if a Raw Binary File (.rbf) is a PR Bitstream File by following the information below. Resolution A PR Bitstream will start with the value 0x97566593 at offset 0x000 AND Have the value 0x5052(PR) at offset 0x00C.Why does the Fitter report that F-Tile FHT supplies must be powered, when my design does not use FHT transceivers in an Agilex® 7 FPGA F‑Tile device compiled in the Quartus® Prime Pro software version 25.3.1 and earlier?
Description Due to a bug in the Quartus® Prime Pro software version 25.3.1 and earlier, the Fitter incorrectly reports that the VCCEHT_FHT_GXF, VCCERT1_FHT_GXF, and VCCERT2_FHT_GXF supplies must be powered, even though your Agilex® 7 FPGA F-Tile device design does not use FHT transceivers. The Agilex 7 FPGA Device Family Pin Connection Guidelines documents for F-Series, I-Series, and M-Series devices states "Tie to GND if there is no FHT channel used" for the VCCEHT_FHT_GXF, VCCERT1_FHT_GXF, and VCCERT2_FHT_GXF supplies. It is safe to power down your supplies in accordance with the Agilex 7 FPGA Device Family Pin Connection Guidelines documents for F-Series, I-Series, and M-Series devices. Resolution This problem will be fixed in a future version of the Quartus Prime Pro software.Why does Partial Reconfiguration (PR) via HPS fail only when using encrypted PR bitstreams?
Description Partial Reconfiguration (PR) via HPS fails only when using encrypted PR bitstreams. This failure only happened on encrypted PR bitstream and not base bitstream. Error message display: root@agilex:~# mv /tmp/pr.rbf /lib/firmware/persona0.rbf root@agilex:~# /usr/bin/dtbt -a /lib/firmware/agilex7_pr_fpga_static_region.dtbo Applying dtbo: /lib/firmware/agilex7_pr_fpga_static_region.dtbo [ 251.625026] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-region/ranges [ 251.638872] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-region/external-fpga-config [ 251.649792] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-region/clocks [ 251.659426] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-region/clock-names [ 251.669543] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/clk_0 [ 251.679105] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/freeze_controller_0 [ 251.693803] of-fpga-region fpga-region:fpga_pr_region0: FPGA Region probed root@agilex:~# /usr/bin/dtbt -a /lib/firmware/agilex7_pr_persona0.dtbo Applying dtbo: /lib/firmware/agilex7_pr_persona0.dtbo [ 262.265981] fpga_manager fpga0: writing persona0.rbf to Stratix10 SOC FPGA Manager [ 267.497950] Stratix10 SoC FPGA manager firmware:svc:fpga-mgr: timeout waiting for svc layer buffers Resolution This problem is scheduled to be fixed in a future release of Quartus® Prime Pro Edition software.