Error: invalid command name "else"

Description

Due to a problem in the Quartus® Prime Pro Edition Software version 25.3.1 and earlier, you might see the error messages below when generating a VHDL simulation model in Platform Designer that includes the Remote Update IP.

Error: invalid command name "else" 
Info: while executing 
Info: "else { 
Info: do_vhdl_sim_cbx altera_remote_update_core 
Info: }" 
Info: (procedure "do_vhdl_sim" line 8) 
Info: invoked from within 
Info: "do_vhdl_sim altera_remote_update_core" 
Error: Generation stopped, 1 or more modules remaining

Resolution

To work around this problem, generate Verilog Simulation Model for Remote Update IP.

This problem is scheduled to be resolved in a future release of the Quartus® Prime Pro Edition Software.