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THuyn18's avatar
THuyn18
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6 years ago

Trouble with programming EPCQ via JTAG interface, cannot find flash loader.

Hello,

I am trying to program an EPCQ4A through an FPGA (10CL006ZE144). When I go to create the .jic file, the flash loader for my FPGA is not listed. The closest I can find is 10CL006Z, and when I create a .jic file using that and try to program it, I get the error:

"Error (209025): Can't recognize silicon ID for device 1. A device's silicon ID is different from its JTAG ID. Verify that all cables are securely connected, select a different device, or check the power on the target system. Make sure the device pins are connected and configured correctly."

What can I do to fix this?

17 Replies

  • a_x_h_75's avatar
    a_x_h_75
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    6 years ago

    That's the correct device to select when creating your jic file.

    What hardware are you using? Given the device you specify I guess it's your own custom hardware.

    Can you program the FPGA directly, using the sof, via JTAG? I think this is more likely to be a signal integrity issue.

    Cheers,

    Alex

    • THuyn18's avatar
      THuyn18
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      6 years ago

      Hi Alex,

      I'm using the USB Blaster II, and I can program the FPGA with a .sof without any issues.

      Thanks,

      Tin

    • THuyn18's avatar
      THuyn18
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      6 years ago

      After taking another look at my board schematic, I noticed that the 3 MSEL pins are grounded. Could this be the problem? I remember reading somewhere that the FPGA must be set to active serial to program an EPCQ device, but I'm not sure where.

    • THuyn18's avatar
      THuyn18
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      6 years ago

      Thanks! I'll get that fix and update on how it works out.

    • THuyn18's avatar
      THuyn18
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      6 years ago

      Update: I got the board reworked so that the MSEL pins were 010, which corresponds to AS, and still got the same error. Will keep troubleshooting and updating.

    • THuyn18's avatar
      THuyn18
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      6 years ago

      What is the difference between standard and fast POR delay? Could that make a difference? I currently have it configured to standard.

    • THuyn18's avatar
      THuyn18
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      6 years ago

      Hi Wolfgang,

      I tried it and nothing changed. Am I supposed to recreate the jic file after changing the frequency?

      Tin

  • a_x_h_75's avatar
    a_x_h_75
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    6 years ago

    You don't need to regenerate the .jic when you change the JTAG frequency.

    Fast & slow POR change the speed at which the device comes up. Doesn't come into play until the devices boot from FLASH.

    How far from the FPGA is the EPSQ? Have you a source termination resistor on DCLK?

    Cheers,

    Alex

    • THuyn18's avatar
      THuyn18
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      6 years ago

      The EPCQ is about 2 in. away from the FPGA. And there is no termination resistor on the DCLK. Should there be one? It didn't mention it in the handbook.

      Tin

  • ShafiqY_Intel's avatar
    ShafiqY_Intel
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    6 years ago

    Hi THuyn18,

    Have you check your MSEL pin? Did you set it to AS config?

    I afraid you are not set MSEL Pin as Active Serial (AS) configuration.

    Am I supposed to recreate the jic file after changing the frequency?

    No, you no need to change the .jic file.

    Thanks

  • a_x_h_75's avatar
    a_x_h_75
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    6 years ago

    Indeed - no mention of a DCLK resistor in the handbook. I would still recommend one, sited near the FPGA.

    If you haven't already seen it, refer to figure 83 on page 115 of the Cyclone 10 User guide. This clarifies the resistor required. Given how close your EPCQ is to your FPGA the resistor may be critical.

    Cheers,

    Alex

    • THuyn18's avatar
      THuyn18
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      6 years ago

      I don't see a DCLK resistor in that figure. What resistor value would you recommend?

    • THuyn18's avatar
      THuyn18
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      6 years ago

      And this resistor goes from the DCLK line to ground, correct?

  • a_x_h_75's avatar
    a_x_h_75
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    6 years ago

    A series resistor in the DCLK trace, similar to the resistor in the DATA trace (in figure 83) but sited as near to the FPGA as possible.

    Cheers,

    Alex