Laboratory Exercise 12

I also have a question regarding this lab. When I was trying to the pin assignment, I got this huge list of pins that I needed to assign, like hex display, leds,... Which one's do I need to assign? Is there a pin assignment sheet for this lab? Also, what does it mean for "ready_signals" to be asserted? Does that mean we raise the value to high or something?

I don't understand what this mean,

"The first element of the buffer is always visible on the readdata left andreaddata right outputs when the read ready signal is asserted. The next element can be read by asserting the

read signal, which ejects the current sample and a new one appears one or more clock cycles later, if read ready

signal is asserted."

I tried to implement this by using if statement and process, but I don't they want us to use them since you have to include libraries to do that, and they won't work in that code.

Any ideas?

Thanks.

Many thanks, itself everything understood.

Why such forum of the response is necessary on that not to wait? Оr here one haughty lazy bastards who consider to respond below the advantage sit?

BURN IN THE HELL!

I was working through this same lab exercise 12.

This code works ...

writedata_left <= readdata_left;

writedata_right <= readdata_right;

write_s <= '1';

read_s <= '1';

This is fine since it echoes the read-in data to the write-out buffers, and then asserts the write_s and read_s so that the codec knows the read and write are done.

However, that is not all that the exercise asks for. It includes this:

"You should take care to read data from and write data to the Audio CODECInterface only when its ready signals are asserted. "

So I was attempting to work out that second part. However I have found no code that accesses read_ready = '1' or write_ready = '1' that functions. The only thing I've found that works is my simple code above, which doesn't exactly complete what is being asked.

Here is just one example of something that doesn't work, though I've done many many combinations ...

process(CloCK_50)

begin

if read_ready = '1' and write_ready = '1' then

writedata_left <= readdata_left;

writedata_right <= readdata_right;

write_s <= '1';

read_s <= '1';

end if;

end process;

Removing references to write_ready and leaving read_ready, doesn't work. vice versa, doesn't work.

This works, but the references to read/write_ready have been removed.

process(CloCK_50)

begin

--if read_ready = '1' and write_ready = '1' then

writedata_left <= readdata_left;

writedata_right <= readdata_right;

write_s <= '1';

read_s <= '1';

--end if;

end process;

Hi, I haven't look at the schematic of the board neither functionnal chronogram nor truth table. So I may be wrong.

But it sounds quite trivial : read data from one component and write data to an other component. Even if we talk about one component : codec but it can be considered as 2 independant components : coder and decoder.

In your code above, you wrote process(clock_50) but clock_50 is not used in the process.

First draw a very simple schema with D flip flops and translate it to VHDL. VHDL is a hardware description language.

You spent too much time by trying to make it work by "trial and error".

I hope the board is functionnal ;-)

-- one clocked process to read data from codec
process(CloCK_50)
begin
if rising_edge(clock_50) then
   if read_ready = '1' then 
      -- ...
      read_s <= '1';
   end if;
end if;
end process;
-- one other process to write data to codec
process(CloCK_50)
begin
if rising_edge(clock_50) then
   if write_ready = '1' then
      writedata_left <= readdata_left;
      writedata_right <= readdata_right;
      write_s <= '1';
   end if;
end if;
end process;

@sethjones : could you put the scheme

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Hi, I haven't look at the schematic of the board neither functionnal chronogram nor truth table. So I may be wrong.

But it sounds quite trivial : read data from one component and write data to an other component. Even if we talk about one component : codec but it can be considered as 2 independant components : coder and decoder.

In your code above, you wrote process(clock_50) but clock_50 is not used in the process.

First draw a very simple schema with D flip flops and translate it to VHDL. VHDL is a hardware description language.

You spent too much time by trying to make it work by "trial and error".

I hope the board is functionnal ;-)

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I agree that it sounds trivial, and when written trivially it works. Yet as soon as I check read_ready or write_ready, it fails.

The board is working fine, it is a new DE2-115 board. Without checking read_ready and write_ready the code echoes audio in to out as expected. Clear and at full volume.

Referencing process(Clock_50) makes no difference, I can ignore it or not, the code works or doesn't work only based on read_ready or write_ready. I just put that Clock_50 in so I could add a "process" statement (and in turn an 'if' statement to check read_ready) and not get a compile error. I've tried making the process dependent on other signals. It works or doesn't only based on read/write_ready.

I've tried code similar to what you've got above, two separate processes, one reading and one writing. I added an extra variable so that the reading process could pull the data in when it was available and the write process had somewhere to write it out from. It made sense, but I was using read_ready and write_ready, so none of it worked. As soon as make my code dependent on read_ready and write_ready, it fails.

It would be nice if someone with a DE2-115 board and more experience than I've got could run a real test, or else message me the official solution so I could try that and see what I'm missing. I would really love to see a verified working solution that references read_ready/write_ready, as the lab requires.

Hi, Whoua ! lots of trials.

Nice to get it works, you may be lucky.

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I've tried making the process dependent on other signals.

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Mostly VHDL design employ process(reset_n, clock) and other combinational logics. The clocked process insure that the design IS SYNCHRONOUS.

Making a design by using only combinational logics needs very (too) much rigorousness (to avoid glitches, latches, ringing....). I think 0.000000001% work with this.

If you make the process dependent on other signals, you build combinational logics. :-(

Maybe Read_ready and write_ready are asserted low !? Sometimes there are errors in manuals.

Hello,

for my application i need to store the digital data from CODEC into on-chip memeory, can any one let help with some example.