Laboratory Exercise 12

Hi, I haven't look at the schematic of the board neither functionnal chronogram nor truth table. So I may be wrong.

But it sounds quite trivial : read data from one component and write data to an other component. Even if we talk about one component : codec but it can be considered as 2 independant components : coder and decoder.

In your code above, you wrote process(clock_50) but clock_50 is not used in the process.

First draw a very simple schema with D flip flops and translate it to VHDL. VHDL is a hardware description language.

You spent too much time by trying to make it work by "trial and error".

I hope the board is functionnal ;-)

-- one clocked process to read data from codec
process(CloCK_50)
begin
if rising_edge(clock_50) then
   if read_ready = '1' then 
      -- ...
      read_s <= '1';
   end if;
end if;
end process;
-- one other process to write data to codec
process(CloCK_50)
begin
if rising_edge(clock_50) then
   if write_ready = '1' then
      writedata_left <= readdata_left;
      writedata_right <= readdata_right;
      write_s <= '1';
   end if;
end if;
end process;

@sethjones : could you put the scheme