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Altera_Forum
Honored Contributor
14 years agoLaboratory Exercise 12
Hello, I need a help to solve the first part of exercise 12, Basic Digital Signal Processing. I'm using the libraries provided "lab12_design_files." Insert the following code in the correct ...
Altera_Forum
Honored Contributor
13 years agoI was working through this same lab exercise 12.
This code works ... writedata_left <= readdata_left; writedata_right <= readdata_right; write_s <= '1'; read_s <= '1'; This is fine since it echoes the read-in data to the write-out buffers, and then asserts the write_s and read_s so that the codec knows the read and write are done. However, that is not all that the exercise asks for. It includes this: "You should take care to read data from and write data to the Audio CODECInterface only when its ready signals are asserted. " So I was attempting to work out that second part. However I have found no code that accesses read_ready = '1' or write_ready = '1' that functions. The only thing I've found that works is my simple code above, which doesn't exactly complete what is being asked. Here is just one example of something that doesn't work, though I've done many many combinations ... process(CloCK_50) begin if read_ready = '1' and write_ready = '1' then writedata_left <= readdata_left; writedata_right <= readdata_right; write_s <= '1'; read_s <= '1'; end if; end process; Removing references to write_ready and leaving read_ready, doesn't work. vice versa, doesn't work. This works, but the references to read/write_ready have been removed. process(CloCK_50) begin --if read_ready = '1' and write_ready = '1' then writedata_left <= readdata_left; writedata_right <= readdata_right; write_s <= '1'; read_s <= '1'; --end if; end process;