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Altera_Forum's avatar
Altera_Forum
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13 years ago

Laboratory Exercise 12

Hello, I need a help to solve the first part of exercise 12, Basic Digital Signal Processing. I'm using the libraries provided "lab12_design_files." Insert the following code in the correct ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Hi, Whoua ! lots of trials.

Nice to get it works, you may be lucky.

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I've tried making the process dependent on other signals.

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Mostly VHDL design employ process(reset_n, clock) and other combinational logics. The clocked process insure that the design IS SYNCHRONOUS.

Making a design by using only combinational logics needs very (too) much rigorousness (to avoid glitches, latches, ringing....). I think 0.000000001% work with this.

If you make the process dependent on other signals, you build combinational logics. :-(

Maybe Read_ready and write_ready are asserted low !? Sometimes there are errors in manuals.