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torstein18's avatar
torstein18
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10 hours ago

Unstable fpga programming using HPS(Agilex3)

Hi

I have a problem where the fpga programming sometime fail when using the overlay method described here under "Reconfiguring Core Fabric from Linux": 

https://altera-fpga.github.io/rel-25.3.1/embedded-designs/agilex-3/c-series/boot-examples/ug-linux-boot-agx3/#reconfiguring-core-fabric-from-u-boot


Here I have first two successful attempt then it fail on the third:

root@agilex3:~# rmdir /sys/kernel/config/device-tree/overlays/0 ; sleep 1 ; mkdir /sys/kernel/config/device-tree/overlays/0 ; cd /lib/firmware/ ; sleep 1; echo overlay.dtb >/sys/kernel/config/device-tree/overlays/0/path
rmdir: '/sys/kernel/config/device-tree/overlays/0': No such file or directory
[  182.671913] fpga_manager fpga0: writing overlay.rbf to Stratix10 SOC FPGA Manager
[  184.865664] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-region/firmware-name
[  184.876007] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-region/config-complete-timeout-us
root@agilex3:/lib/firmware# rmdir /sys/kernel/config/device-tree/overlays/0 ; sleep 1 ; mkdir /sys/kernel/config/device-tree/overlays/0 ; cd /lib/firmware/ ; sleep 1; echo overlay.dtb >/sys/kernel/config/device-tree/overlays/0/path
[  196.530735] fpga_manager fpga0: writing overlay.rbf to Stratix10 SOC FPGA Manager
[  198.659279] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-region/firmware-name
[  198.669650] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-region/config-complete-timeout-us
root@agilex3:/lib/firmware# rmdir /sys/kernel/config/device-tree/overlays/0 ; sleep 1 ; mkdir /sys/kernel/config/device-tree/overlays/0 ; cd /lib/firmware/ ; sleep 1; echo overlay.dtb >/sys/kernel/config/device-tree/overlays/0/path
[  214.383163] fpga_manager fpga0: writing overlay.rbf to Stratix10 SOC FPGA Manager
[  217.508857] arm-smmu-v3 16000000.iommu: CMD_SYNC timeout at 0x00004405 [hwprod 0x00004408, hwcons 0x00004405]
[  217.509907] arm-smmu-v3 16000000.iommu: CMD_SYNC timeout at 0x00004407 [hwprod 0x00004408, hwcons 0x00004405]

U-Boot SPL 2025.10 (May 18 2026 - 08:34:29 +0000)
Reset state: Cold
MPU           800000 kHz
L4 Main       400000 kHz
L4 sys free   100000 kHz
L4 MP         200000 kHz
L4 SP         100000 kHz
SDMMC         200000 kHz
init_mem_cal: Initial DDR calibration IO96B_0 succeed
DDR: Calibration success
is_mailbox_spec_compatible: IOSSM mailbox version: 1
LPDDR4: 1792 MiB
ecc_interrupt_status: ECC error number detected on IO96B_0: 0
SDRAM-ECC: Initialized success

Does anybody know how to debug and fix this?

I'm using Quartus Prime Version 25.3.0 Build 109
Devboard: DK-A3W135BM16AEA: Agilex™ 3 FPGA and SoC C-Series Development Kit

Arm Processor

2 Replies

  • torstein18's avatar
    torstein18
    Icon for New Contributor rankNew Contributor
    9 hours ago
    root@agilex3:~# rmdir /sys/kernel/config/device-tree/overlays/0 ; sleep 1 ; mkdir /sys/kernel/config/device-tree/overlays/0 ; cd /lib/firmware/ ; sleep 1; echo overlay.dtb >/sys/kernel/config/device-tree/overlays/0/path
rmdir: '/sys/kernel/config/device-tree/overlays/0': No such file or directory
[   36.922294] fpga_manager fpga0: writing overlay.rbf to Stratix10 SOC FPGA Manager
[   39.120291] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-region/firmware-name
[   39.130686] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-region/config-complete-timeout-us
root@agilex3:/lib/firmware# rmdir /sys/kernel/config/device-tree/overlays/0 ; sleep 1 ; mkdir /sys/kernel/config/device-tree/overlays/0 ; cd /lib/firmware/ ; sleep 1; echo overlay.dtb >/sys/kernel/config/device-tree/overlays/0/path
[   45.737387] fpga_manager fpga0: writing overlay.rbf to Stratix10 SOC FPGA Manager
[   47.872751] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-region/firmware-name
[   47.886499] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-region/config-complete-timeout-us
root@agilex3:/lib/firmware# rmdir /sys/kernel/config/device-tree/overlays/0 ; sleep 1 ; mkdir /sys/kernel/config/device-tree/overlays/0 ; cd /lib/firmware/ ; sleep 1; echo overlay.dtb >/sys/kernel/config/device-tree/overlays/0/path
[   56.264190] fpga_manager fpga0: writing overlay.rbf to Stratix10 SOC FPGA Manager
[   59.386742] arm-smmu-v3 16000000.iommu: CMD_SYNC timeout at 0x00004449 [hwprod 0x0000444a, hwcons 0x00004449]
[   60.461430] arm-smmu-v3 16000000.iommu: CMD_SYNC timeout at 0x0000444b [hwprod 0x0000444c, hwcons 0x00004449]
[   61.536055] arm-smmu-v3 16000000.iommu: CMD_SYNC timeout at 0x0000444d [hwprod 0x0000444e, hwcons 0x00004449]
[   62.610600] arm-smmu-v3 16000000.iommu: CMD_SYNC timeout at 0x0000444f [hwprod 0x00004450, hwcons 0x00004449]
[   63.685144] arm-smmu-v3 16000000.iommu: CMD_SYNC timeout at 0x00004451 [hwprod 0x00004452, hwcons 0x00004449]
[   64.759689] arm-smmu-v3 16000000.iommu: CMD_SYNC timeout at 0x00004453 [hwprod 0x00004454, hwcons 0x00004449]
[   64.769798] socfpga-dwmac 10830000.ethernet eth0: NETDEV WATCHDOG: CPU: 1: transmit queue 7 timed out 6452 ms
[   65.844646] arm-smmu-v3 16000000.iommu: CMD_SYNC timeout at 0x00004455 [hwprod 0x00004456, hwcons 0x00004449]
[   66.919264] arm-smmu-v3 16000000.iommu: CMD_SYNC timeout at 0x00004457 [hwprod 0x00004458, hwcons 0x00004449]
[   66.934688] socfpga-dwmac 10830000.ethernet eth0: Reset adapter.

U-Boot SPL 2025.10 (May 18 2026 - 08:34:29 +0000)
Reset state: Cold
MPU           800000 kHz
L4 Main       400000 kHz
L4 sys free   100000 kHz
L4 MP         200000 kHz
L4 SP         100000 kHz
SDMMC         200000 kHz
init_mem_cal: Initial DDR calibration IO96B_0 succeed
DDR: Calibration success
is_mailbox_spec_compatible: IOSSM mailbox version: 1
LPDDR4: 1792 MiB
ecc_interrupt_status: ECC error number detected on IO96B_0: 0
SDRAM-ECC: Initialized success

     

  • torstein18's avatar
    torstein18
    Icon for New Contributor rankNew Contributor
    10 hours ago

    In the original design everything run on a 100 MHz clock input fpga_clk_100, when I use this the programming is stable and work every time, but I need more than one clock in my design so I connected the fpga_clk_100 to a pll and used the output clock from the pll in the design, then the programming became unstable. Does anybody understand why? The output clock from the pll is also 100MHz