Unstable fpga programming using HPS(Agilex3)

In the original design everything run on a 100 MHz clock input fpga_clk_100, when I use this the programming is stable and work every time, but I need more than one clock in my design so I connected the fpga_clk_100 to a pll and used the output clock from the pll in the design, then the programming became unstable. Does anybody understand why? The output clock from the pll is also 100MHz