To evaluate and monitor CPU frequency behavior in the Kernel OS

Question

We need to verify CPU frequency behaviour straight from the Linux kernel because we are currently working with a customised Agilex 5 System-on-Module (SOM). Ensuring appropriate frequency scaling and governor functionality under a range of workloads is our aim. Would you kindly provide guidance regarding the device tree modifications, kernel configurations, and testing methods needed to enable and validate CPU frequency scaling on this platform? I would be very grateful for any advice or reference materials that are specific to Agilex 5.

annak_altera · Answer

Hi Arun,In the arm64 config you can see the CPU_FREQ options which will help you implement governor functionality with frequency scaling: https://github.com/altera-fpga/linux-socfpga/blob/socfpga-6.12.33-lts/arch/arm64/configs/defconfigYour kernel will look for operating points in your device tree to set available frequencies. Here is an idea of what the implementation could look like:cpu0: cpu@0 {
    ...
    operating-points-v2 = &lt;&amp;cpu_opp_table&gt;;
    ...
};

...

cpu_opp_table: opp-table {
    compatible = "operating-points-v2";
    opp-1000000000 {
        opp-hz = /bits/ 64 &lt;1000000000&gt;;
        opp-microvolt = &lt;950000&gt;;
    };
    opp-1400000000 {
        opp-hz = /bits/ 64 &lt;1400000000&gt;;
        opp-microvolt = &lt;1050000&gt;;
    };
};After reboot you can use the /sys/devices/system/cpu/cpu0/cpufreq utilities to check available governors, frequencies, and watch how the CPU responds to stress.

arun_prabakatr · Answer

Hi AnnaK_AlteraThanks for the guidance. We've enabled the relevant CONFIG_CPU_FREQ options in our arm64 kernel config and included #include "socfpga_agilex5.dtsi" in our device tree, which contains all the necessary CPU-related nodes including TSC and others.However, after reboot, the /sys/devices/system/cpu/cpu0/cpufreq directory is still not appearing. We've also updated our kernel log file to help identify what might be missing. Could you please take a look and let us know if there's anything we've overlooked?Thanks again for your support.

jamesg_altera · Answer

Hi Arun_Prabakatr,The source of all CPU clocks in an Agilex 5 system on chip is the Clock Manager. You can find some details about it here:https://www.intel.com/content/www/us/en/docs/programmable/814346/25-3/clock-manager.htmlYou will find information about the Linux driver for the Clock Manager here:https://altera-fpga.github.io/rel-25.3/linux-embedded/drivers/clock_manager/clock_manager/

jamesg_altera · Answer

Hi Arun_Prabakatr,Here is some further information on this topic. The Linux driver for clock manager does not support modifying the clock frequency, only reading it. As described in the HPS Technical Reference Manual here...https://www.intel.com/content/www/us/en/docs/programmable/814346/25-3/clock-manager-programming-model.html... there are two supported ways of configuring clock frequencies for the HPS subsystem, including the CPU clocks:Configure in the Parameters section of the HPS IP in Quartus Platform Designer before building the FPGA imageConfigure clock manager register settings in the bootloader, before starting LinuxSection 7.7 of the document goes on to give example register settings for different scenarios. Section 7.8 has details of the relevant registers: https://www.intel.com/content/www/us/en/docs/programmable/814346/25-3/clock-manager-address-map-and-register-49571.htmlIf you find this information helpful, please mark it as the accepted solution.

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To evaluate and monitor CPU frequency behavior in the Kernel OS

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