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Occasional ContributorStratix 10 HPS to 25G ethernet interface
How can we interface Stratix 10 HPS and 25G ethernet IP core. Is there any reference design for this? How to switch between 10G and 25G based on user selection. What should be the reference frequency for the 25G ip.
3 Replies
umut_arrowNew Contributor
I believe Stratix 10 HPS is capable of 10/100/1000 Mb, not 10G/25G.
1.19.1. Key Features of the Intel Stratix 10 HPS • Stratix 10 TX Device Overview • Altera Documentation and Resources CenterYou may have seen this already, but there's a 25G reference design, but it's connected to the fabric.
1. 25G Ethernet Intel FPGA IP Quick Start Guide • 25G Ethernet Stratix 10 Intel FPGA IP Design Example User Guide • Altera Documentation and Resources Center
Sajeev_antonywe plan to use the 25G Ethernet Stratix 10 IP with MAC+PCS+PMA. We are using this to conenct to a gransmaster cllock for PTP time sync. We have enabled IEEE 1588 in the IP core. also have enabled Enable 10G/25G dynamic rate switching.
We want to know,
- How to controll the switch between 10G and 25G.
- How to interface the 25G IP to the Stratix 10 HPS.
We do not need 25G throughput, just need the phyical interface for IEEE 1588 time sync messaging.
- umut_arrow
Are you using the E-tile on Stratix 10TX or L-tile/H-tile?
If latter, please see the IP guide below for 25G ethernet below. You need the channel_reset port for dynamic switching. It shouldn't be complicated to control the ATX PLLs dynamically to switch between 10G and 25G with a reset.
In terms of interfacing it with the HPS, perhaps you can route 25G's MAC Avalon through HPS with a bridge. I've found a Stratix 10 SoC 10G 1588 PTP design example. Perhaps this design example can point you to a solution.https://www.rocketboards.org/foswiki/Projects/Stratix10SoCDesignExampleFor10GbeWithIEEE1588PTPCapability
