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AJama4's avatar
AJama4
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Running bare-metal from SDRAM memory. Error

I am using De1-SoC board. Cyclone V (Cortex-A9). As far as I understand the base address of the SDRAM memory in the MPU address space is 0x00100000 and the ending address is 0xC0000000 by default. Its written in the TR-manual in the system interconnect chapter. My question is why am I getting an error when I try to load a simple program to the SDRAM memory with following scatter file configuration?

SDRAM 0x00100000 0x02000000 ;

{

APP_CODE + 0

{

* (+ RO , + RW , + ZI )

}

ARM_LIB_STACKHEAP 0x000800000 EMPTY 0x000100000 ; Application heap and stack

{ }

}

ERROR:

ERROR(CMD16-TAD11-NAL22):

! Failed to load "HelloWorldARM.axf"

! Failed to write 3,132 bytes to address S:0x00100000

! General error on memory or register access.

One reason could be that the SDRAM is not configured but I am already running a preloader before loading my bare-metal program. Any hints??

16 Replies

  • Hi,

    During the preloader, did you see the SDRAM calibrated successfully?

    It should look something like this:

    CALIBRATION PASSED

    SDRAM: 1024 MiB

    Regards

  • AJama4's avatar
    AJama4
    Icon for Occasional Contributor rankOccasional Contributor

    Hi,

    Following appears in the SERIAL TERMINAL:

    U-Boot SPL 2013.01.01 (Jul 01 2019 - 14:31:08)

    BOARD : Altera SOCFPGA Cyclone V Board

    CLOCK: EOSC1 clock 25000 KHz

    CLOCK: EOSC2 clock 25000 KHz

    CLOCK: F2S_SDR_REF clock 0 KHz

    CLOCK: F2S_PER_REF clock 0 KHz

    CLOCK: MPU clock 800 MHz

    CLOCK: DDR clock 400 MHz

    CLOCK: UART clock 100000 KHz

    CLOCK: MMC clock 50000 KHz

    CLOCK: QSPI clock 400000 KHz

    RESET: COLD

    INFO : Watchdog enabled

    SDRAM: Initializing MMR registers

    SDRAM: Calibrating PHY

    SEQ.C: Preparing to start memory calibration

    SEQ.C: CALIBRATION PASSED

    SDRAM: 1024 MiB

    ALTERA DWMMC: 0

    Card did not respond to voltage select!

    spl: mmc init failed: err - -17

    ### ERROR ### Please RESET the board ###

    • EBERLAZARE_I_Intel's avatar
      EBERLAZARE_I_Intel
      Icon for Regular Contributor rankRegular Contributor

      Hi,

      The initial error is is from the SDRAM memory controller not being configured properly during preloader.

      Looking at the error of the log:

      Card did not respond to voltage select!

      spl: mmc init failed: err - -17

      You are using SD card to boot the board? If yes, may I know the part number?

      Regards.

  • AJama4's avatar
    AJama4
    Icon for Occasional Contributor rankOccasional Contributor

    I am not using the SD Card instead, I am using DS5 debugger to load the preloader.

    I was using the standard preloader of GHRD that was included with the board support package. How can I change the preloader to configure it properly?

    Regards,

  • Hi,

    To generate and compile the preloader I highly recommend you check here (For Cyclone V), in Procedure tab there are also Screenshots of the procedure for your reference to guide you better:

    https://rocketboards.org/foswiki/Documentation/GSRDPreloader

    In general, you could also check other topics/tasks for Cyclone V such as compiling the Hardware Design etc.:

    https://rocketboards.org/foswiki/Main/GettingStarted

    From above link, choose your board, Cyclone > then your Quartus Version > Task you interested in.

  • AJama4's avatar
    AJama4
    Icon for Occasional Contributor rankOccasional Contributor

    I have generated two separate preloaders for two separate Quartus projects but in the end the serial terminal's output is the same when I try to load the preloader using DS5 debugger.I think I didn't ask my question clearly. My question is, if its not working with the standard GHRD preloader for the De1-SoC board, then how can I change the settings or what additional should I do? I know already the whole procedure how to generate the preloader using BSP-editor and its various options.

    • EBERLAZARE_I_Intel's avatar
      EBERLAZARE_I_Intel
      Icon for Regular Contributor rankRegular Contributor

      Hi,

      Assuming you have generated the preloaders correctly;

      1) Can you check the BSEL pins of the board if they have been set properly?

  • AJama4's avatar
    AJama4
    Icon for Occasional Contributor rankOccasional Contributor

    Hello,

    BSEL switch is absent so the setting is the default one by Terrasic.

    • EBERLAZARE_I_Intel's avatar
      EBERLAZARE_I_Intel
      Icon for Regular Contributor rankRegular Contributor

      Hi,

      Can you load the preloader first to make sure the SDRAM has been calibrated successfully? Only then you are to create and apply the scatter file, since the SDRAM has been brought up from preloader.

      Replying back to your first posts, can you direct me to the TR-manual which demonstrate the scatter file that you mentioned?

      This is the link to locate the bare metal application in the SDRAM by creating a new scatter file, is this the examples you tried to follow?:

      https://www.intel.com/content/www/us/en/programmable/documentation/lro1424280108409.html#lro1424311442722

      • AJama4's avatar
        AJama4
        Icon for Occasional Contributor rankOccasional Contributor

        Hi,

        The scatter file was being written by me after reading the default SDRAM base address (starting) and ending address in MPU address space. I am first loading the preloader and then trying to run the bare-metal.

        I have already followed the aforementioned example and its not working.

        After, making some changes, now my preloader works fine without error; but still the bare.metal program doesn't load from the SDRAM.

        Here is the output in the terminal (for preloader):

        U-Boot SPL 2013.01.01 (Aug 27 2019 - 08:37:10)

        BOARD : Altera SOCFPGA Cyclone V Board

        CLOCK: EOSC1 clock 25000 KHz

        CLOCK: EOSC2 clock 25000 KHz

        CLOCK: F2S_SDR_REF clock 0 KHz

        CLOCK: F2S_PER_REF clock 0 KHz

        CLOCK: MPU clock 925 MHz

        CLOCK: DDR clock 400 MHz

        CLOCK: UART clock 100000 KHz

        CLOCK: MMC clock 50000 KHz

        CLOCK: QSPI clock 370000 KHz

        RESET: COLD

        SDRAM: Initializing MMR registers

        SDRAM: Calibrating PHY

        SEQ.C: Preparing to start memory calibration

        SEQ.C: CALIBRATION PASSED

        SDRAM: 1024 MiB

        SDRAM: Ensuring specified SDRAM size is correct ...passed

        SDRAM: Running EMIF Diagnostic Test ...Passed

  • ESaiv's avatar
    ESaiv
    Icon for New Contributor rankNew Contributor

    Hi. I am having this identical issue. Were you able to resolve it? I can appreciate that this was some time ago.