ContributorWhat is the limit on how many pins can be used between the HPS and FPGA? Is there any availability for custom pin definitions here?
Thanks,
K
Hi K606,
Please refer to this document: https://www.intel.com/content/www/us/en/docs/programmable/813934/24-3/general-purpose-i-o-overview.html and see if it answers your questions.
Sue
ContributorHi K606,
Can you be more specific about what device you are using, whether you are routing from the HPS to the FPGA or FPGA to HPS? Have you done a google search on this question?
Sue
ContributorHi K606,
Please refer to this document: https://www.intel.com/content/www/us/en/docs/programmable/813934/24-3/general-purpose-i-o-overview.html and see if it answers your questions.
Sue
ContributorHi there,
Sorry yes forgot to mention - it is the Agilex 5.
Ideally both directions - so for I have seen some docs on the register map, but these are all pre-defined pins. Are there any open ones?
ModeratorHi @606,
Greetings, as solution has been marked from the mention doubts, hence would assume challenge are overcome.
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