Forum Discussion

Contributor

6 months ago

Solved

Pins

What is the limit on how many pins can be used between the HPS and FPGA? Is there any availability for custom pin definitions here? Thanks, K

Hps Boot

SueC_Altera
6 months ago
Hi K606,
Please refer to this document: https://www.intel.com/content/www/us/en/docs/programmable/813934/24-3/general-purpose-i-o-overview.html and see if it answers your questions.
Sue

SueC_Altera

Contributor

6 months ago

Hi K606,

Can you be more specific about what device you are using, whether you are routing from the HPS to the FPGA or FPGA to HPS? Have you done a google search on this question?

Sue

Forum Discussion

Pins

Recent Discussions

Unique ID registers in Cyclone V

Audio interface with Agilex 5 A5ED065BB32AI4S

Operating system kernel-level FPGA bridge communication

Routing PL DDR to PS

Validating ECC Functionality on Custom Agilex 5 SOM in Linux Kernel