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K606
Contributor
ContributorPins
What is the limit on how many pins can be used between the HPS and FPGA? Is there any availability for custom pin definitions here? Thanks, K
Hi K606,
Please refer to this document: https://www.intel.com/content/www/us/en/docs/programmable/813934/24-3/general-purpose-i-o-overview.html and see if it answers your questions.
Sue
K606Contributor
ContributorHi there,
Sorry yes forgot to mention - it is the Agilex 5.
Ideally both directions - so for I have seen some docs on the register map, but these are all pre-defined pins. Are there any open ones?
