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sunyeong's avatar
sunyeong
Icon for New Contributor rankNew Contributor
2 years ago
Solved

How to program FPGA in Arria 10 HPS?

Hello, I'm reading the below rocketboards document about how to program an FPGA from HPS. GSRD131ProgrammingFPGA According to this document, rbf file is little differnt with Arria10. It seems ...
Hps Boot
Hps Debug
Sw Development
  • aikeu's avatar
    aikeu
    2 years ago

    Hi sunyeong,


    You can refer to this document on building the bootloader method using Arria10:

    https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10


    Arria 10 FPGA configuration is done in two steps:

    Configuration of periphery(periph.rbf): this allows HPS DDRAM to be brought up, and must do be done in SPL

    Configuration of fabric(core.rbf): it configures the actual FPGA core fabric, and can be done from SPL or U-Boot


    Thanks.

    Regards,

    Aik Eu


aikeu's avatar
aikeu
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi sunyeong,


Sorry that I do not understand about the naming of the rbf which you mentioned in your previous statement.

The latest building bootloader for Arria10 will require the periph.rbf for the DDR to work first in order to boot up properly.

The core.rbf will be your FPGA design.

the periph.rbf and the core.rbf can be combined into a single file which is fit_spl_fpga.itb

The below is the QSPI flash memory location to be flashed with different files used as a Golden reference software design(GSRD) for socfpga booting:


"

quartus_hps -c 1 -o pv -a 0x0000000 u-boot-splx4.sfp

(first stage bootloader where DDR will be calibrated with periph.rbf being configured.)


quartus_hps -c 1 -o pv -a 0x0100000 fit_uboot.itb

(second stage bootloader where you will able to enter Uboot user space)


quartus_hps -c 1 -o pv -a 0x0300000 fit_spl_fpga.itb

(consist of the configuration files(periph.rbf + core.rbf) which will be used in booting. Can consider a seperate configuration file which only consist of periph.rbf referring to the #Option 1 in the building bootlolader document)


quartus_hps -c 1 -o pv -a 0x1200000 kernel.itb

(Linux kernel related)


quartus_hps -c 1 -o pv -a 0x2720000 core-image-minimal-arria10-rootfs.jffs2

(Linux kernel related)


"


Can check the repo content for Uboot and Linux kernel in the github link below:

https://github.com/altera-opensource


Thanks.

Regards,

Aik Eu


  • sunyeong's avatar
    sunyeong
    Icon for New Contributor rankNew Contributor
    2 years ago

    Hi, Aik Eu.

    Thanks for your comments.

    Okay, I understand that you mentioned.

    core.rbf: related to FPGA design

    periph.rbf: related to DDR to work first in order to boot up properly.

    I previously mentioned that there is an error in u-boot.

    The logic of uploading rbf files was skipped because of mismatch configuration name. But error log is not printed.

    (u-boot-socfpga/drivers/fpga/socfpga_arria10.c)

    static int first_loading_rbf_to_buffer(struct udevice *dev,
				struct fpga_loadfs_info *fpga_loadfs,
				u32 *buffer, size_t *buffer_bsize,
				size_t *buffer_bsize_ori)
{
//...

	for (i = 0; i < count; i++) {
		images_noffset = fit_conf_get_prop_node_index(buffer_p,
							     confs_noffset,
							     FIT_FPGA_PROP, i);
		uname = fit_get_name(buffer_p, images_noffset, NULL);
		if (uname) {
			debug("FPGA: %s\n", uname);

			if (strstr(uname, "fpga-periph") && // "fpga-periph-1" in fit_spl_fpga.its
				(!is_fpgamgr_early_user_mode() ||
				is_fpgamgr_user_mode() ||
				is_periph_program_force())) {
				fpga_node_name = uname;
				printf("FPGA: Start to program ");
				printf("peripheral/full bitstream ...\n");
				break;
			} else if (strstr(uname, "fpga-core") && // "fpga-core-1" in fit_spl_fpga.its
					(is_fpgamgr_early_user_mode() &&
					!is_fpgamgr_user_mode())) {
				fpga_node_name = uname;
				printf("FPGA: Start to program core ");
				printf("bitstream ...\n");
				break;
			}
		}
		schedule();
	}
	
	if (!fpga_node_name) {//foga_node_name is null.
		debug("FPGA: No suitable bitstream was found, count: %d.\n", i);//because of log level, this log is not printed.
		return 1;
	}
//...
}

    Don't care about that.

    I am trying to upload rbf files using u-boot command.

    This is related to #option1 that you mentioned.

    The documentation explains how to upload rbf files using sd card.

    But, I can't use sdmmc dauter card, and I am using QSPI boot mode.

    So, Is there any way to load rbf files using usb?

    Thank you.

    Regards,

    Jung.

    • sunyeong's avatar
      sunyeong
      Icon for New Contributor rankNew Contributor
      2 years ago

      Hi, Aik Eu.

      I use tftp command for uploading rbf file.

      tftp ${loadaddr} fit_spl_fpga.itb
imxtract ${loadaddr} fpga-core ${coreaddr}
fpga load 0 ${coreaddr} ${filesize}

      The document that you mentioned said that should upload core.rbf file.

      But, in u-boot, uploading core.rbf file is skipped because of below code.

      (u-boot-socfpga/drivers/fpga/socfpga_arria10.c)

      /* This function is used to load the core bitstream from the OCRAM. */
int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
{
//...
	if (rbfinfo.section == core_section &&
		!(is_fpgamgr_early_user_mode() && !is_fpgamgr_user_mode())) {
		debug("FPGA : Must be in early release mode to program ");
		debug("core bitstream.\n");
		return -EPERM;
	}
//...
}

      Which rbf file should I upload? (core.rbf? periph.rbf?)

      I tried periph.rbf, it works properly without error log.

      Thanks.

      Regards,

      Jung.