Forum Discussion
enable bridge crashes Linux
- 11 months ago
So, I think I made some progress.
- I enable the bridges in Barebox by setting the status and bridge-enable properties.
- In the Linux devicetree overlay, I only set the status property, not the bridge-enable property.
The Barebox DT (the "0x1" syntax matters, it seems):
&fpga_bridge0 { status = "okay"; bridge-enable = <0x1>; };The Linux DT overlay:
/dts-v1/; /plugin/; / { fragment@0 { target = <&base_fpga_region>; __overlay__ { #address-cells = <0x1>; #size-cells = <0x1>; // The .rbf file must be placed in /lib/firmware firmware-name = "soc_firwmare.rbf"; fpga-bridges = <&fpga_bridge0 &fpga_bridge1>; }; }; /* Enable the lightweight FPGA to HPS bridge (lwhps2fpga) */ fragment@1 { target = <&fpga_bridge0>; __overlay__ { status = "okay"; // Don't set bridge-enable! // bridge-enable = <1>; }; }; /* Enable the HPS to FPGA bridge (hps2fpga) */ fragment@2 { target = <&fpga_bridge1>; __overlay__ { status = "okay"; // Don't set bridge-enable! // bridge-enable = <1>; }; }; };Then, I when I check the status of the bridges, I get what I expect:
# for f in /proc/device-tree/soc/fpga?bridge*; do echo $(basename $f)":" $(cat $f/status); done fpga-bridge@ff600000: disabled fpga-bridge@ffc25080: disabled fpga_bridge@ff400000: okay fpga_bridge@ff500000: okay #I didn't try to communicate between the HPS and the FPGA yet, but it looks promising.
Hi @dpeng
It looks like the board freeze occurs when the bridge drivers (lwhps2fpga/ hps2fpga) attempt to enable the bridges. Since FPGA programming works but enabling the bridges causes a hang, this is likely due to hardware configuration or base address mismatch between your Terasic boards and the Enclustra SA2 module.
A few suggestions:
Check bridge base addresses in your device tree against the Enclustra SA2 memory map; the addresses may differ from the DE0/ADC-SoC boards.
Verify preloader / handoff settings – the bridges must be properly configured and clocked before enabling them.
Enable one bridge at a time to isolate which one causes the hang.
Reference Enclustra BSP,compare their provided socfpga.dtsi or device tree overlays for correct bridge configuration.
Most hangs in regmap_write() indicate access to an unclocked or unmapped peripheral region. Once the bridge base addresses and clocks match your module, the overlay should work as expected.
If possible, please share the live DT nodes for fpga_bridge0 and fpga_bridge1 after boot but before applying the overlay; that can help pinpoint the issue.
- dpeng1 year ago
Occasional Contributor
About your suggestions:
- Aren't the addresses the same for the whole Cyclone V family?
- As Enclustra's BSP is really outdated (U-Boot and Linux), I've been working to port the SA2 SoM to Barebox. So, that's definitely something to look at. It copied the handoff files from Enclustra's reference design that matches my hardware. If I get it correctly, you say that Barebox DT must match Platform Designer settings? Can't the bridges be configured in Linux DT only?
- Sure. I posted the whole overlay to show what I'm trying to do.
- OK, I'll look at it.
The live tree for nodes fpga_bridge0 and fpga_bridge1:
// fpga_bridge0: fpga_bridge@ff400000 { compatible = "altr,socfpga-lwhps2fpga-bridge"; clocks = <0x05>; resets = <0x06 0x61>; status = "disabled"; phandle = <0x49>; reg = <0xff400000 0x100000>; }; // fpga_bridge1: fpga_bridge@ff500000 { compatible = "altr,socfpga-hps2fpga-bridge"; clocks = <0x05>; resets = <0x06 0x60>; status = "disabled"; phandle = <0x4a>; reg = <0xff500000 0x10000>; };and the whole live DT: https://paste.debian.net/1392376/