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dpeng

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Re: Cyclone V: how to boot Linux from QSPI?
Hi, Sorry for not replying, but I was busy with some another thing. I did not solve this issue. My goal is to create an image with genimage, so the whole process will be automated. I'm having trouble creating the configuration file for genimage. Also, why is the pre-loader split in 4 chunks?
2 months ago Place SoC System
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Cyclone V: how to boot Linux from QSPI?
I am building a system with Buildroot and Barebox as the bootloader. I can generate a working SD card image. Now, I want to transpose this to a 64MiB NOR QSPI flash on the SoM. I read the HPS boot guide, that describes the required SD card partition layout, but it is not very verbose about the QSPI... I read that UBI + UBIFS is very common for NOR flash. I understand that it is well suited for the rootfs. But where should I place the pre-loader? Could someone give more details to install Linux on a QSPI and boot from it?
3 months ago Place SoC System
Hps Boot
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Re: enable bridge crashes Linux
So, I think I made some progress. I enable the bridges in Barebox by setting the status and bridge-enable properties. In the Linux devicetree overlay, I only set the status property, not the bridge-enable property. The Barebox DT (the "0x1" syntax matters, it seems): &fpga_bridge0 { status = "okay"; bridge-enable = <0x1>; }; The Linux DT overlay: /dts-v1/; /plugin/; / { fragment@0 { target = <&base_fpga_region>; __overlay__ { #address-cells = <0x1>; #size-cells = <0x1>; // The .rbf file must be placed in /lib/firmware firmware-name = "soc_firwmare.rbf"; fpga-bridges = <&fpga_bridge0 &fpga_bridge1>; }; }; /* Enable the lightweight FPGA to HPS bridge (lwhps2fpga) */ fragment@1 { target = <&fpga_bridge0>; __overlay__ { status = "okay"; // Don't set bridge-enable! // bridge-enable = <1>; }; }; /* Enable the HPS to FPGA bridge (hps2fpga) */ fragment@2 { target = <&fpga_bridge1>; __overlay__ { status = "okay"; // Don't set bridge-enable! // bridge-enable = <1>; }; }; }; Then, I when I check the status of the bridges, I get what I expect: # for f in /proc/device-tree/soc/fpga?bridge*; do echo $(basename $f)":" $(cat $f/status); done fpga-bridge@ff600000: disabled fpga-bridge@ffc25080: disabled fpga_bridge@ff400000: okay fpga_bridge@ff500000: okay # I didn't try to communicate between the HPS and the FPGA yet, but it looks promising.
3 months ago Place SoC System
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Re: enable bridge crashes Linux
@JitLoonL_Altera, I enabled the bridge driver in Barebox: CONFIG_FPGA=y CONFIG_FPGA_BRIDGE=y CONFIG_SOCFPGA_FPGA_BRIDGE=y And the bridge in Barebox: &fpga_bridge0 { status = "okay"; bridge-enable = <0x1>; }; Barebox boot log (note the "altera-hps2fpga-bridge" lines): barebox 2025.07.0 #2 Thu Aug 28 15:09:04 CEST 2025 Board: Enclustra Mercury+ SA2 netconsole: registered as netconsole-1 altera-hps2fpga-bridge ff400000.fpga_bridge@ff400000.of: enabling bridge altera-hps2fpga-bridge ff400000.fpga_bridge@ff400000.of: fpga bridge [lwhps2fpga] registered socfpga_designware_eth ff702000.ethernet@ff702000.of: user ID: 0x10, Synopsys ID: 0x37 mdio_bus: miibus0: probed dw_mmc ff704000.mmc@ff704000.of: registered as mmc0 cadence_qspi ff705000.spi@ff705000.of: couldn't determine block-size cadence_qspi ff705000.spi@ff705000.of: probing for flashchip failed cadence_qspi ff705000.spi@ff705000.of: Cadence QSPI NOR probe failed malloc space: 0x1ff00000 -> 0x3fdfffff (size 511 MiB) mmc0: detected SD card version 2.0 mmc0: registered mmc0 eth0: got preset MAC address: 20:b0:f7:0a:6c:08 Hit any to stop autoboot: 1 barebox@Enclustra Mercury+ SA2:/ But the system still hangs when I apply the DT overlay.
3 months ago Place SoC System
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Re: enable bridge crashes Linux
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3 months ago Place SoC System
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Re: enable bridge crashes Linux
I noticed that in Barebox, the clock used in the default configuration of "fpga_bridge0" is enabled by default: barebox@Enclustra Mercury+ SA2:/ clk_dump l4_main_clk osc1 (rate 50000000, enable_count: 4, enabled) main_pll@40 (rate 1600000000, enable_count: 3, always enabled) mainclk@4c (rate 400000000, enable_count: 1, always enabled) l4_main_clk (rate 400000000, enable_count: 1, enabled) On the other hand, the one that's used by the lw-h2f bridge in Platform Designer is disabled. I can enable it manually but it doesn't fix the crash. barebox@Enclustra Mercury+ SA2:/ clk_dump h2f_user2_clk osc1 (rate 50000000, enable_count: 3, enabled) sdram_pll@c0 (rate 800000000, enable_count: 0, always enabled) h2f_usr2_clk@d4 (rate 50000000, enable_count: 0, always enabled) h2f_user2_clk (rate 50000000, enable_count: 0, enabled) barebox@Enclustra Mercury+ SA2:/ clk_enable h2f_user2_clk barebox@Enclustra Mercury+ SA2:/ clk_dump h2f_user2_clk osc1 (rate 50000000, enable_count: 4, enabled) sdram_pll@c0 (rate 800000000, enable_count: 1, always enabled) h2f_usr2_clk@d4 (rate 50000000, enable_count: 1, always enabled) h2f_user2_clk (rate 50000000, enable_count: 1, enabled) "h2f_usr2_clk@d4" is the parent of "h2f_user2_clk". I'm not sure which one I should use in the DTs (Barebox and Linux) as the clock of "fpga_bridge0". I tried both. But applying the overlay still crashes the system.
4 months ago Place SoC System
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Re: enable bridge crashes Linux
I am not able to dump the live tree after I apply the overlay that enables the bridge, because the system freezes totally at this step. This is precisely what I'm trying to fix. In the project, i.e. the Mercury+ SA2 ST1 Reference Design, the Platform Designer setup looks like this: I checked that the handoff files in Barebox are up to date with the design. In the Barebox DT, I added these lines, just like in the Linux DT: &fpga_bridge0 { clocks = <&h2f_user2_clk>; }; I confirmed that the clock is changed by dumping the live tree and before applying the overlay. I'm trying to enable the bridge in a Linux overlay: fragment@1 { target = <&fpga_bridge0>; __overlay__ { status = "okay"; bridge-enable = <1>; }; }; But applying the overlay keeps freezing the system.
4 months ago Place SoC System
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Re: enable bridge crashes Linux
I noticed that in Platform Designer, the h2f_lw_axi_clock input signal takes its source from h2f_user2_clock. But the LW H2F bridge clock was &l4_main_clk. So I changed it in the Linux DT (not the overlay), like this: &fpga_bridge0 { clocks = <&h2f_user2_clk>; }; I could check the change in the live DT, but it didn't solve the issue.
4 months ago Place SoC System
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Re: enable bridge crashes Linux
Hi @JitLoonL_Altera About your suggestions: Aren't the addresses the same for the whole Cyclone V family? As Enclustra's BSP is really outdated (U-Boot and Linux), I've been working to port the SA2 SoM to Barebox. So, that's definitely something to look at. It copied the handoff files from Enclustra's reference design that matches my hardware. If I get it correctly, you say that Barebox DT must match Platform Designer settings? Can't the bridges be configured in Linux DT only? Sure. I posted the whole overlay to show what I'm trying to do. OK, I'll look at it. The live tree for nodes fpga_bridge0 and fpga_bridge1: // fpga_bridge0: fpga_bridge@ff400000 { compatible = "altr,socfpga-lwhps2fpga-bridge"; clocks = <0x05>; resets = <0x06 0x61>; status = "disabled"; phandle = <0x49>; reg = <0xff400000 0x100000>; }; // fpga_bridge1: fpga_bridge@ff500000 { compatible = "altr,socfpga-hps2fpga-bridge"; clocks = <0x05>; resets = <0x06 0x60>; status = "disabled"; phandle = <0x4a>; reg = <0xff500000 0x10000>; }; and the whole live DT: https://paste.debian.net/1392376/
4 months ago Place SoC System
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enable bridge crashes Linux
Hi, We selected a Cyclone V SoC FPGA for our project. I started on Terasic demo boards (DE0 and ADC-SoC). On these boards, that both bear a Cyclone V (P/N 5CSEMA4U23C6N), I could, with a devicetree overlay, program the FPGA from Linux and enable the lwh2f and h2f bridges. Now that we are developing a custom board, we bought an Enclustra SA2 SoM, with a Cyclone V (P/N 5CSTFD6D5F31I7N). I am trying to apply the DT overlay on socfpga.dtsi. /dts-v1/; /plugin/; / { fragment@0 { target = <&base_fpga_region>; // #address-cells = <0x1>; // #size-cells = <0x1>; __overlay__ { #address-cells = <0x1>; #size-cells = <0x1>; ranges = < // The .rbf file must be placed in /lib/firmware firmware-name = "soc_firwmare.rbf"; fpga-bridges = <&fpga_bridge0 &fpga_bridge1>; }; }; /* Enable the lightweight FPGA to HPS bridge (lwhps2fpga) */ fragment@1 { target = <&fpga_bridge0>; __overlay__ { status = "okay"; bridge-enable = <1>; }; }; /* Enable the HPS to FPGA bridge (hps2fpga) */ fragment@2 { target = <&fpga_bridge1>; __overlay__ { status = "okay"; bridge-enable = <1>; }; }; }; But since I switched to the SA2 module, the board freezes when `fragment@1` or `fragment@2` is not commented in the overlay. If I comment out the `status = "okay"` lines, the board does boot and the FPGA is programmed. By dumping the live tree, I can see that the `bridge-enable` property appears under the expected node. dtc gives no warning nor errors. I added some debug messages ("DEBUG >>") in the kernel code, and I could see that the crash happens in some function called by regmap_write(), in regmap.c. [ 2.632673] altera_hps2fpga_bridge ff400000.fpga_bridge: enabling bridge [ 2.639397] altera_hps2fpga_bridge ff400000.fpga_bridge: DEBUG >> Before _alt_hps2fpga_enable_set() [ 2.648424] _alt_hps2fpga_enable_set() DEBUG >> bridge brought out of reset [ 2.655377] _alt_hps2fpga_enable_set() DEBUG >> make bridge visible to L3 masters [ 2.662832] _alt_hps2fpga_enable_set() DEBUG >> spinlock acquired [ 2.668902] _alt_hps2fpga_enable_set() DEBUG >> before regmap_write() [ 2.675315] regmap_write() DEBUG >> start of regmap_write() [ 2.680865] regmap_write() DEBUG >> lock acquired [ 2.685550] _regmap_write() DEBUG >> start [ 2.689632] _regmap_write() DEBUG >> writable [ 2.693971] _regmap_write() DEBUG >> before reg_write() [ 2.699173] _regmap_write() context=0xc18d2e00, reg=0, val=0x00000011 [ 2.705598] _regmap_bus_reg_write() DEBUG >> start [ 2.710371] _regmap_bus_reg_write() after _regmap_range_lookup() [ 2.716352] _regmap_bus_reg_write() DEBUG >> after regmap_reg_addr() [ 2.722679] _regmap_bus_reg_write() DEBUG >> map->bus_context=0xc1b31980, reg=0, val=0x00000011 Now, I'm really stuck.
Solved
4 months ago Place SoC System
Sw Development
3.3KViews
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