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dpeng

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Re: Cyclone V: how to enable USB1 with a ULPI USB PHY (USB3320)?
Hi Alan, Thanks for giving it a thought. I finally got it working: a misconfigured switch. No comments, please... David
1 month ago Place SoC System
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Cyclone V: how to enable USB1 with a ULPI USB PHY (USB3320)?
I want to enable USB1 (USB 2.0 controller) of the Cyclone V in host-only mode. But Vbus is not present and no device is detected. A ULPI-compatible Microchip USB3320 USB PHY is connected to the Cyclone V with a ULPI interface. The CPEN pin of the USB3320 controls a power switch on the board. To enable the 5V Vbus voltage, used to power USB devices, the CPEN pin must be driven high. Its POR state is low. HPS_GPIO0 is connected to the active-low RESET# pin of the USB3320. To check if Vbus is on, I connected a mouse, that should light up when connected to a USB host. The main DT file is socfpga.dtsi. I altered it a little in both Barebox and Linux v6.6.22: &usbphy0 { reset-gpios = <&porta 0 GPIO_ACTIVE_LOW>; status = "okay"; }; &usb1 { status = "okay"; dr_mode = "host"; }; Barebox shows that GPIO0 (RESET#) is an output and is high, which is OK: barebox:/ gpioinfo ff708000.gpio@ff708000:gpio-controller@0.of GPIOs 454-482, chip ff708000.gpio@ff708000:gpio-controller@0.of: dir val requested name label GPIO 0: out hi active low soc:usbphy.of reset GPIO 1: in lo false GPIO 2: in lo false Barebox shows that the dwc2 driver binds to usb1: barebox@Enclustra Mercury+ SA2:/ drvinfo dwc2 Driver Device(s) -------------------- dwc2 ffb40000.usb@ffb40000.of Linux boot log: # dmesg | grep -Ei 'usb|dwc2' [ 0.042372] usbcore: registered new interface driver usbfs [ 0.042408] usbcore: registered new interface driver hub [ 0.042448] usbcore: registered new device driver usb [ 0.896138] usbcore: registered new interface driver usb-storage [ 0.920377] usbcore: registered new interface driver usbhid [ 0.932106] usbhid: USB HID core driver [ 1.086689] usb_phy_generic soc:usbphy: dummy supplies not allowed for exclusive requests [ 1.095129] dwc2 ffb40000.usb: supply vusb_d not found, using dummy regulator [ 1.111913] dwc2 ffb40000.usb: supply vusb_a not found, using dummy regulator [ 1.137639] dwc2 ffb40000.usb: DWC OTG Controller [ 1.142362] dwc2 ffb40000.usb: new USB bus registered, assigned bus number 1 [ 1.149465] dwc2 ffb40000.usb: irq 48, io mem 0xffb40000 [ 1.155604] hub 1-0:1.0: USB hub found I was told that the "dummy regulator" messages are nothing to worry about. More Linux commands: # lsusb Bus 001 Device 001: ID 1d6b:0002 Linux 6.6.22 dwc2_hsotg DWC OTG Controller # gpioinfo gpiochip0 gpiochip0 - 29 lines: line 0: unnamed "reset" output active-low [used] line 1: unnamed unused input active-high line 2: unnamed unused input active-high Pastebin my configuration: https://paste.debian.net/hidden/77078877 Buildroot defconfig: https://paste.debian.net/hidden/e8b1d0fc Linux defconfig: https://paste.debian.net/hidden/d578d0f9
Solved
1 month ago Place SoC System
embedded peripheral
operating system
63Views
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Re: Cyclone V: how to boot Linux from QSPI?
Hi, Sorry for not replying, but I was busy with some another thing. I did not solve this issue. My goal is to create an image with genimage, so the whole process will be automated. I'm having trouble creating the configuration file for genimage. Also, why is the pre-loader split in 4 chunks?
4 months ago Place SoC System
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Cyclone V: how to boot Linux from QSPI?
I am building a system with Buildroot and Barebox as the bootloader. I can generate a working SD card image. Now, I want to transpose this to a 64MiB NOR QSPI flash on the SoM. I read the HPS boot guide, that describes the required SD card partition layout, but it is not very verbose about the QSPI... I read that UBI + UBIFS is very common for NOR flash. I understand that it is well suited for the rootfs. But where should I place the pre-loader? Could someone give more details to install Linux on a QSPI and boot from it?
5 months ago Place SoC System
Hps Boot
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Re: enable bridge crashes Linux
So, I think I made some progress. I enable the bridges in Barebox by setting the status and bridge-enable properties. In the Linux devicetree overlay, I only set the status property, not the bridge-enable property. The Barebox DT (the "0x1" syntax matters, it seems): &fpga_bridge0 { status = "okay"; bridge-enable = <0x1>; }; The Linux DT overlay: /dts-v1/; /plugin/; / { fragment@0 { target = <&base_fpga_region>; __overlay__ { #address-cells = <0x1>; #size-cells = <0x1>; // The .rbf file must be placed in /lib/firmware firmware-name = "soc_firwmare.rbf"; fpga-bridges = <&fpga_bridge0 &fpga_bridge1>; }; }; /* Enable the lightweight FPGA to HPS bridge (lwhps2fpga) */ fragment@1 { target = <&fpga_bridge0>; __overlay__ { status = "okay"; // Don't set bridge-enable! // bridge-enable = <1>; }; }; /* Enable the HPS to FPGA bridge (hps2fpga) */ fragment@2 { target = <&fpga_bridge1>; __overlay__ { status = "okay"; // Don't set bridge-enable! // bridge-enable = <1>; }; }; }; Then, I when I check the status of the bridges, I get what I expect: # for f in /proc/device-tree/soc/fpga?bridge*; do echo $(basename $f)":" $(cat $f/status); done fpga-bridge@ff600000: disabled fpga-bridge@ffc25080: disabled fpga_bridge@ff400000: okay fpga_bridge@ff500000: okay # I didn't try to communicate between the HPS and the FPGA yet, but it looks promising.
5 months ago Place SoC System
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Re: enable bridge crashes Linux
@JitLoonL_Altera, I enabled the bridge driver in Barebox: CONFIG_FPGA=y CONFIG_FPGA_BRIDGE=y CONFIG_SOCFPGA_FPGA_BRIDGE=y And the bridge in Barebox: &fpga_bridge0 { status = "okay"; bridge-enable = <0x1>; }; Barebox boot log (note the "altera-hps2fpga-bridge" lines): barebox 2025.07.0 #2 Thu Aug 28 15:09:04 CEST 2025 Board: Enclustra Mercury+ SA2 netconsole: registered as netconsole-1 altera-hps2fpga-bridge ff400000.fpga_bridge@ff400000.of: enabling bridge altera-hps2fpga-bridge ff400000.fpga_bridge@ff400000.of: fpga bridge [lwhps2fpga] registered socfpga_designware_eth ff702000.ethernet@ff702000.of: user ID: 0x10, Synopsys ID: 0x37 mdio_bus: miibus0: probed dw_mmc ff704000.mmc@ff704000.of: registered as mmc0 cadence_qspi ff705000.spi@ff705000.of: couldn't determine block-size cadence_qspi ff705000.spi@ff705000.of: probing for flashchip failed cadence_qspi ff705000.spi@ff705000.of: Cadence QSPI NOR probe failed malloc space: 0x1ff00000 -> 0x3fdfffff (size 511 MiB) mmc0: detected SD card version 2.0 mmc0: registered mmc0 eth0: got preset MAC address: 20:b0:f7:0a:6c:08 Hit any to stop autoboot: 1 barebox@Enclustra Mercury+ SA2:/ But the system still hangs when I apply the DT overlay.
5 months ago Place SoC System
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Re: enable bridge crashes Linux
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5 months ago Place SoC System
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Re: enable bridge crashes Linux
I noticed that in Barebox, the clock used in the default configuration of "fpga_bridge0" is enabled by default: barebox@Enclustra Mercury+ SA2:/ clk_dump l4_main_clk osc1 (rate 50000000, enable_count: 4, enabled) main_pll@40 (rate 1600000000, enable_count: 3, always enabled) mainclk@4c (rate 400000000, enable_count: 1, always enabled) l4_main_clk (rate 400000000, enable_count: 1, enabled) On the other hand, the one that's used by the lw-h2f bridge in Platform Designer is disabled. I can enable it manually but it doesn't fix the crash. barebox@Enclustra Mercury+ SA2:/ clk_dump h2f_user2_clk osc1 (rate 50000000, enable_count: 3, enabled) sdram_pll@c0 (rate 800000000, enable_count: 0, always enabled) h2f_usr2_clk@d4 (rate 50000000, enable_count: 0, always enabled) h2f_user2_clk (rate 50000000, enable_count: 0, enabled) barebox@Enclustra Mercury+ SA2:/ clk_enable h2f_user2_clk barebox@Enclustra Mercury+ SA2:/ clk_dump h2f_user2_clk osc1 (rate 50000000, enable_count: 4, enabled) sdram_pll@c0 (rate 800000000, enable_count: 1, always enabled) h2f_usr2_clk@d4 (rate 50000000, enable_count: 1, always enabled) h2f_user2_clk (rate 50000000, enable_count: 1, enabled) "h2f_usr2_clk@d4" is the parent of "h2f_user2_clk". I'm not sure which one I should use in the DTs (Barebox and Linux) as the clock of "fpga_bridge0". I tried both. But applying the overlay still crashes the system.
5 months ago Place SoC System
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Re: enable bridge crashes Linux
I am not able to dump the live tree after I apply the overlay that enables the bridge, because the system freezes totally at this step. This is precisely what I'm trying to fix. In the project, i.e. the Mercury+ SA2 ST1 Reference Design, the Platform Designer setup looks like this: I checked that the handoff files in Barebox are up to date with the design. In the Barebox DT, I added these lines, just like in the Linux DT: &fpga_bridge0 { clocks = <&h2f_user2_clk>; }; I confirmed that the clock is changed by dumping the live tree and before applying the overlay. I'm trying to enable the bridge in a Linux overlay: fragment@1 { target = <&fpga_bridge0>; __overlay__ { status = "okay"; bridge-enable = <1>; }; }; But applying the overlay keeps freezing the system.
6 months ago Place SoC System
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Re: enable bridge crashes Linux
I noticed that in Platform Designer, the h2f_lw_axi_clock input signal takes its source from h2f_user2_clock. But the LW H2F bridge clock was &l4_main_clk. So I changed it in the Linux DT (not the overlay), like this: &fpga_bridge0 { clocks = <&h2f_user2_clk>; }; I could check the change in the live DT, but it didn't solve the issue.
6 months ago Place SoC System
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