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dpeng's avatar
dpeng
Icon for Occasional Contributor rankOccasional Contributor
1 year ago
Solved

enable bridge crashes Linux

Hi, We selected a Cyclone V SoC FPGA for our project. I started on Terasic demo boards (DE0 and ADC-SoC). On these boards, that both bear a Cyclone V (P/N 5CSEMA4U23C6N), I could, with a devicetree ...
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  • dpeng's avatar
    dpeng
    11 months ago

    So, I think I made some progress.

    1. I enable the bridges in Barebox by setting the status and bridge-enable properties.
    2. In the Linux devicetree overlay, I only set the status property, not the bridge-enable property.

    The Barebox DT (the "0x1" syntax matters, it seems):

    &fpga_bridge0 {
	status = "okay";
	bridge-enable = <0x1>;
};

    The Linux DT overlay:

    /dts-v1/;
/plugin/;

/ {
	fragment@0 {
		target = <&base_fpga_region>;

		__overlay__ {
			#address-cells = <0x1>;
			#size-cells = <0x1>;

			// The .rbf file must be placed in /lib/firmware
			firmware-name = "soc_firwmare.rbf";
			fpga-bridges = <&fpga_bridge0 &fpga_bridge1>;
		};
	};

	/* Enable the lightweight FPGA to HPS bridge (lwhps2fpga) */
	fragment@1 {
		target = <&fpga_bridge0>;

		__overlay__ {
			status = "okay";
			// Don't set bridge-enable!
			// bridge-enable = <1>;
		};
	};

	/* Enable the HPS to FPGA bridge (hps2fpga) */
	fragment@2 {
		target = <&fpga_bridge1>;

		__overlay__ {
			status = "okay";
			// Don't set bridge-enable!
			// bridge-enable = <1>;
		};
	};
};

    Then, I when I check the status of the bridges, I get what I expect:

    # for f in /proc/device-tree/soc/fpga?bridge*; do echo $(basename $f)":" $(cat $f/status); done
fpga-bridge@ff600000: disabled
fpga-bridge@ffc25080: disabled
fpga_bridge@ff400000: okay
fpga_bridge@ff500000: okay
#

    I didn't try to communicate between the HPS and the FPGA yet, but it looks promising.

dpeng's avatar
dpeng
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

I noticed that in Barebox, the clock used in the default configuration of "fpga_bridge0" is enabled by default:

barebox@Enclustra Mercury+ SA2:/ clk_dump l4_main_clk
osc1 (rate 50000000, enable_count: 4, enabled)
    main_pll@40 (rate 1600000000, enable_count: 3, always enabled)
        mainclk@4c (rate 400000000, enable_count: 1, always enabled)
            l4_main_clk (rate 400000000, enable_count: 1, enabled)

On the other hand, the one that's used by the lw-h2f bridge in Platform Designer is disabled. I can enable it manually but it doesn't fix the crash.

barebox@Enclustra Mercury+ SA2:/ clk_dump h2f_user2_clk
osc1 (rate 50000000, enable_count: 3, enabled)
    sdram_pll@c0 (rate 800000000, enable_count: 0, always enabled)
        h2f_usr2_clk@d4 (rate 50000000, enable_count: 0, always enabled)
            h2f_user2_clk (rate 50000000, enable_count: 0, enabled)
barebox@Enclustra Mercury+ SA2:/ clk_enable h2f_user2_clk
barebox@Enclustra Mercury+ SA2:/ clk_dump h2f_user2_clk
osc1 (rate 50000000, enable_count: 4, enabled)
    sdram_pll@c0 (rate 800000000, enable_count: 1, always enabled)
        h2f_usr2_clk@d4 (rate 50000000, enable_count: 1, always enabled)
            h2f_user2_clk (rate 50000000, enable_count: 1, enabled)

"h2f_usr2_clk@d4" is the parent of "h2f_user2_clk". I'm not sure which one I should use in the DTs (Barebox and Linux) as the clock of "fpga_bridge0". I tried both. But applying the overlay still crashes the system.