Contributor
Regular ContributorHi Brian,
There is no definitive answer for the maximum frequency of the F2SDRAM bridge.
For Cyclone V, F2SDRAM bridge access is managed by the SDRAM subcontroller system, and the operating frequency for the L3 Interconnect, which the F2SDRAM bridge uses has a maximum clock rate of 400 MHz for the -1V speed grade.
https://www.intel.com/content/www/us/en/docs/programmable/683801/current/hps-clock-performance.html
The available throughput is shared among all F2SDRAM bridges instantiated in the system. As more bridges are added, we will need to reduce the input frequency to ensure reliable operation and to stay within the total bandwidth limits.
Please also note that the above calculation is theoretical. In practice, real-world throughput may be lower due to various system factors.
Regards
Jingyang, Teh
ContributorPlease use "@" to reply the system did not email notification.
For this explanation, it is not given out the possible cause of stall on distro.
In order for system stall the sdram data must be runed or corrupted.
However with proper address R/W there is no way to trigger such action.
So why during boot or when system is stable once the high throughput write
could introduce this issue?
Could you provide a check method for L3/L4 is enable?
I think there maybe cache that is not turned on?
