Cyclone V HPS FPGA2SDRAM Clock Queries

tehjingy_Altera​ 

Ok, more info for this situation.

KEY 1: If data is kept reading on f2h_sdram0 148M no issue is found.

Once the f2h_sdram1 is enable via some control and start stream at 144M the system stall on distro.

However, the data r/w on bus f2h_sdram0 andf2h_sdram1 are functioning properly.

The only issue is the system aka the CPU is stall and terminal no longer response.

The most interesting thing is that the background FPGA fabric are all functioning like free-run w/o any stall or data stuck.

Well the same design with only slowing down the f2h_sdram1 from 144M to 100M fixed all the issue.

f2h_sdram0 <- mostly read

f2h_sdram1 <- mostly write

So when 144M is used onf2h_sdram1 and once the CPU is stall. All data read / write are still working.
read streams write streams are all functioning via some interface to verify.

Brian