Contributor
Occasional ContributorOK... I still don't quite understand your point. Please let me ask you some more questions...
Why do you think "the AXI3 64bit only support 1 set "?
Based on the link, the table mentioned : 64bit AXI uses "2 Command Ports, 1 Read Ports, 1 Write Ports".
The FPGA-HPS SDRAM interface has six command ports, four read ports, and four write ports, and taking the above into account, we can create three 64-bit AXI interfaces. In this case, six(=2x3) command ports, three(=1x3) read ports, and three3(=1x3) write ports are utilized. (In this case, no more bus interfaces can be created, since all 6 command ports are used.)
This can be also confirmed with HPS Qsys as below:
Could you please elaborate a bit more on what exactly you mean by "this information is mislabeled"?
Thanks,
ContributorQuestion 1: why it is 1 set:
Rely: based on this site the table labeled "possible port utilization" only shown 1 set of bus rather than maximum # of co-exist bus on the same settings.
https://www.intel.com/content/www/us/en/docs/programmable/683360/18-0/fpga-to-hps-sdram-access.html
The title "possible port utilization" I am not sure this is what the table have completely shown.
i.e. only 1 set of 64bit AXI3 etc.
This is why I mentioned you miss my point on the ticket.
What those examples you shown are computed rather than follow the table info.
Which also does not mentioned via equations nor co-exist bus examples.
This is why this is so puzzling and simply using Qsys alone only shows two 256 AXI3 returns error.
Then in order to know what caused this error also confused from the site that only 1 set of AXI3 64bit possible port utilization from the table.
