Contributor
ContributorNo you still misunderstand what i am trying to point out.
I do clearly known the HPS can only create "1" 256 bit AXI3 R/W interface based on the fixed HPS interface.
Either from the HPS Qsys or the link I enclosed from first place.
However, based on the link, the table mentioned "possible port utilization".
Why the AXI3 64bit only support 1 set?
With the above statement AXI3 allow what configurations?
What I am trying to pointed out is this information is labeled wrongly and very puzzling from first place.
Occasional ContributorOK... I still don't quite understand your point. Please let me ask you some more questions...
Why do you think "the AXI3 64bit only support 1 set "?
Based on the link, the table mentioned : 64bit AXI uses "2 Command Ports, 1 Read Ports, 1 Write Ports".
The FPGA-HPS SDRAM interface has six command ports, four read ports, and four write ports, and taking the above into account, we can create three 64-bit AXI interfaces. In this case, six(=2x3) command ports, three(=1x3) read ports, and three3(=1x3) write ports are utilized. (In this case, no more bus interfaces can be created, since all 6 command ports are used.)
This can be also confirmed with HPS Qsys as below:
Could you please elaborate a bit more on what exactly you mean by "this information is mislabeled"?
Thanks,
