Cyclone V HPS bus - FPGA-to-SDRAM

@BrianSune_Froum ,

Thank you for your responses and clarifications.

To understand how to interpret the numbers in the table, could you please read this section?

"12.4.4. FPGA-to-HPS SDRAM Interface" (Cyclone V HPS Technical Reference Manual)

https://www.intel.com/content/www/us/en/docs/programmable/683126/21-2/fpga-to-hps-sdram-interface-36440.html

The FPGA‑to‑HPS SDRAM bridge has 6 command ports, 4 read ports and 4 write ports. In the FPGA‑to‑HPS SDRAM bridge, an Avalon-MM/AXI bus interface is formed by combining these ports according to the table.

: How many 256bit AXI interfaces can be generated in the FPGA‑to‑HPS SDRAM bridge?

With referring to the table, a 256bit AXI interface uses 2 command ports, 4 read ports and 4 write ports.

Since the FPGA‑to‑HPS SDRAM interface has 6 command ports, 4 read ports and 4 write ports, you can generate ONE 256bit AXI interface.

Hope this clears up your doubts.

Regards,