avalon mm stimulus

Hello s002wjhwen

Yes, inside Altera Quartus Platform Designer, Altera has a dedicated, built-in library called the Avalon Verification IP (VIP) Suite designed specifically for this.

These are native Platform Designer components that you can search for in the IP Catalog window on the left side of your screen.

1. The Generator (Traffic / Command Driver)

To generate raw traffic (Reads/Writes) over Avalon-MM, look for:

• IP Catalog Name: Avalon-MM Master Agent or Avalon-MM Master Bus Functional Model (BFM)

• What it does: It provides a programmable master interface. In your simulation testbench, it gives you a clean API of SystemVerilog/Verilog tasks (such as push_command(), set_command_address(), and set_command_data()) to forcefully inject read and write traffic into your system fabric.

2. The Monitor & Checker (Protocol Validation)

To monitor the bus and catch timing or protocol violations, look for:

• IP Catalog Name: Avalon-MM Monitor

• What it does: You splice this component directly onto any existing Avalon-MM link (between any master and slave). It acts as a passive listener.

• The Checker Mechanism: It contains embedded SystemVerilog Assertions (SVA). If a master changes an address while waitrequest is high, or if a slave drops data prematurely, the Monitor automatically catches it and prints a protocol violation error directly to your simulator transcript.

How to add them to your Platform Designer System

1. Open Platform Designer.

2. In the IP Catalog search bar, type Avalon Verification.

3. Double-click Avalon-MM Master BFM (Generator) or Avalon-MM Monitor (Checker) to add them to your system.

4. Export or wire their clock, reset, and Avalon interfaces to the hardware blocks you want to test.

Accessing the Raw Code

When you click Generate HDL... inside Platform Designer, Quartus spits out the completely unencrypted, raw source files into your project directory.

If you navigate into your generated system folders, you will find:

• altera_avalon_mm_master_bfm.v (The raw Verilog generator)

• altera_avalon_mm_monitor.sv (The raw SystemVerilog protocol checker)

You can view these files directly to see how Altera handles the state machines and assertions