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LironAvrhmov's avatar
LironAvrhmov
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7 hours ago

Arria 10 HPS - DMA EMAC reset issue

Hello,

We are bring-up the custom Arria 10 board, we have some issue with HPS GMAC in U-Boot.

Arria 10 connect to SFP (1 G Ethernet) , our interface is :

HPS EMAC0 → FPGA GMII-to-SGMII Converter → SFP (SGMII PHY)

We are working without MDC/MDIO , in fixed mode.

During our testing we performed ping and after this we read register 0xFF801000 and we received value 0x00020101( Last bit DMA_BUS_MODE.SWR = 1 instead of the 0).

We checked :

  1. The input clock of 125 MHz  by oscilloscope - looks ok.
  2. Reset Manager:  0xFFD05024 = 0xFF7FBEBE (EMAC0 is released from reset).

  3. Bridge is working.

  4. GMII-to-SGMII registers are accessible

  5.  Device tree addresses were verified agaonst the .sopcinfo file

Looking forward to your response, thanks in advance.

 

 

 

 

Arm Processor
embedded peripheral
Hps Arch
operating system

1 Reply

  • HectorC_Altera's avatar
    HectorC_Altera
    Icon for New Contributor rankNew Contributor
    1 hour ago

    Hi LironAvrhmov​ ,

    The software reset triggered by DMA_BUS_MODE.SWR happens in the TX and RX clock domains. DMA_BUS_MODE.SWR will de-assert it self only after the the reset sequence has completed on all GMAC clock domains.

    A common cause for this issue is that  emac_clk_rx_i and emac_clk_tx_i (clocks from external PHY) are not free running at the time of the SWR assertion. Also, as you are using the Fabric interface you need to have all the soft logic out of reset before bringing up the Ethernet interfaces in u-boot, which I think you have as bridges and GMII-to-SGMII registers are accesible.

    As a general rule, check that your system is fulfilling all the requirements listed in here.

    To confirm if the clocks from the PHY are ok, you can do a signal tap capture before trying to bring the ethernet interface in u-boot.

    Let me know if you have any question with the provided information.

     

    Regards

    - Hector