New Contributor
New ContributorHi LironAvrhmov ,
The software reset triggered by DMA_BUS_MODE.SWR happens in the TX and RX clock domains. DMA_BUS_MODE.SWR will de-assert it self only after the the reset sequence has completed on all GMAC clock domains.
A common cause for this issue is that emac_clk_rx_i and emac_clk_tx_i (clocks from external PHY) are not free running at the time of the SWR assertion. Also, as you are using the Fabric interface you need to have all the soft logic out of reset before bringing up the Ethernet interfaces in u-boot, which I think you have as bridges and GMII-to-SGMII registers are accesible.
As a general rule, check that your system is fulfilling all the requirements listed in here.
To confirm if the clocks from the PHY are ok, you can do a signal tap capture before trying to bring the ethernet interface in u-boot.
Let me know if you have any question with the provided information.
Regards
- Hector
