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New ContributorARM A9 bare matal IRQ priority can't work
I use cyclone V HPS, and there is a problem in configuring interrupt priority. I gave OSC1 TIMER a higher priority, and after the program was executed, I found that it could not preempt the low priority external interrupt from FPGA. Look at the priority configuration MASK and binary point are lower 3 bits. Excuse me, where is my configuration wrong.
The OSC1 timer runs normally as shown in figure 2. after the interrupt from FPGA is enabled, the timer interrupt cannot run normally, as shown in figure 1
12 Replies
EBERLAZARE_I_IntelRegular Contributor
Hi,
Is the timer interrupt that you mentioned also could not run normal if if interrupt from other sources other than FPGA?
TBaoxI didn't try that.
But IRQ from FPGA timer ip doesn't preempt the low priority external interrupt from FPGA pio,too.
So I think something wrong on my configation.
- EBERLAZARE_I_Intel
May I know which Quartus version you are using? Also how did you compile/setup your preloader files?
- TBaox
Quartus Prime 17.1
and SOC EDS 17.1
- EBERLAZARE_I_Intel
Hi,
Please check the ARM document on the Interrupt prioritization:
You can also check out the example design below on GIC controller:
ftp://ftp.intel.com/pub/fpgaup/pub/Intel_Material/16.0/Tutorials/Using_GIC.pdf
