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TBaox's avatar
TBaox
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5 years ago

ARM A9 bare matal IRQ priority can't work

I use cyclone V HPS, and there is a problem in configuring interrupt priority. I gave OSC1 TIMER a higher priority, and after the program was executed, I found that it could not preempt the low prior...
EBERLAZARE_I_Intel's avatar
EBERLAZARE_I_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

Is the timer interrupt that you mentioned also could not run normal if if interrupt from other sources other than FPGA?

TBaox's avatar
TBaox
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5 years ago

I didn't try that.

But IRQ from FPGA timer ip doesn't preempt the low priority external interrupt from FPGA pio,too.

So I think something wrong on my configation.