Hi Jvsalo,
Thank you for your patience while we looked into your question.
After consulting with our subject matter experts, we have an update regarding your Q1 about possible configuration issues causing the cache line to be flushed to memory instead of being allocated in the HPS cache.
One important detail is the setting of the AxUSER[7:0] signal. To ensure that AXI transactions are routed through the Cache Coherency Unit (CCU) — and not bypassed to DRAM — it is necessary to set:
AxUSER[7:0] = 0x04
This setting explicitly routes the transaction through the CCU path, which is required for cache-coherent behavior on the Agilex 7 platform. Without this, even with correct AWSNOOP and AWCACHE values, the CCU may not handle the transaction as coherent, leading to the unexpected behavior you observed.
You can refer to this in the documentation here:
https://www.intel.com/content/www/us/en/docs/programmable/683567/24-3/ccu-to-memory-cache-allocate-fm-dm.html
Let us know if applying this change helps resolve the latency issue.
as for Q3 we currently don't have an explicit latency measurement for this particular operation.
Regards,
Boon Khai.