New Contributor
Occasional ContributorHi Thank you for waiting,
I'm still working to get input from the subject matter expert(SME) in Altera regarding your question 1 and question 3. But in the mean time can provide the response for Q2 and Q4 based on the current documentation and known issue.
For Q2
- You are right, the hardware bug described is due to the IP Bug in the CCU, where from software perspective, disabling the snoop filter is the only workaround this issue. The snoop filter will benefit when there is a heavy load transaction. like in your case sending small amount of data eg: 1 cache line disabling the snoop filter is unlikely to negatively affect performance, in fact for small cache line the HPS expect fast access, disabling the snoop filter should be more beneficial in your case, improved latency and reliability.
For Q4
- At this time, to the best of my knowledge, there is no fully validated reference design that demonstrates low-latency cache-injected writes from FPGA to HPS L2 cache. That said, I will check with the SMEs to confirm whether there might be an internal example or recommended setup that we can share.
Regards,
Boon Khai.
New ContributorThank you Boon Khai for your efforts so far. This issue is still very relevant for us.
It is good to hear that the CCU bug should not be a problem for us. In that case, I'm still hoping that this is something we can fix by configuration or software.
Don't hesitate to ask any extra information about our setup if needed.
Occasional ContributorHi Jvsalo,
Thank you for your patience while we looked into your question.
After consulting with our subject matter experts, we have an update regarding your Q1 about possible configuration issues causing the cache line to be flushed to memory instead of being allocated in the HPS cache.
One important detail is the setting of the AxUSER[7:0] signal. To ensure that AXI transactions are routed through the Cache Coherency Unit (CCU) — and not bypassed to DRAM — it is necessary to set:
AxUSER[7:0] = 0x04
This setting explicitly routes the transaction through the CCU path, which is required for cache-coherent behavior on the Agilex 7 platform. Without this, even with correct AWSNOOP and AWCACHE values, the CCU may not handle the transaction as coherent, leading to the unexpected behavior you observed.
You can refer to this in the documentation here:
Let us know if applying this change helps resolve the latency issue.
as for Q3 we currently don't have an explicit latency measurement for this particular operation.
Regards,
Boon Khai.
