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eharalanova's avatar
eharalanova
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5 months ago

Agilex 5E - PCIE PERST# pin - failing compilation

Hello! I'm using Critical Link MytiSom Dev Kit. It has the same FPGA as the Altera Dev Kit - A5ED065BB32AE6SR0. I'm adapting the PCIe Root Port example from Altera - I have assigned the PCIe Gen3x4 l...
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eharalanova's avatar
eharalanova
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1 month ago

Hello,

I found out, that the pins BE25 and BM28 are not connected to any reset on the board and are left floating. Can I tie high  pin_perst_n and Pin_perst_n_1 (inputs to the PCIe HIP) in the logic? I use the PCIe in Root Port mode. 
Thank you,
Eleonora

RongY_altera's avatar
RongY_altera
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25 days ago

Normally the perst_n of RP is used to drive perst_n of downstream EP. Given your situation, the only practical option is to tie them HIGH.

 

 

Regards,

Rong