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SarahTr's avatar
SarahTr
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7 months ago

Agilex 5 HPS EMAC2 SWR bit in DMA_Mode Register Not Clearing

Hello,

Following section 5.1.7 of the Agilex 5 Hard Processor System Technical Reference Manual, and based on what I found in U-Boot and Linux, I am writing an Ethernet driver that uses EMAC2 with an RGMII interface. I am currently stuck at the software reset using the SWR bit of the DMA_Mode register, as it remains set to 1.

Our boot flow on the AXE5-Eagle board is ATF -> U-Boot -> our OS. We use the U-Boot from https://github.com/ArrowElectronics/u-boot-socfpga/tree/socfpga_v2025.07 with some adaptations to load our OS instead of Linux.

When I read the DMA_Mode register before performing any EMAC setup in our OS, I already see the value set to 1. After bringing the PHY out of reset and setting the SWR bit again, it does not clear.

I also tried putting the EMAC into reset using the per0modrst register, setting the System Manager tsn2 register to 1 again, and then bringing the EMAC out of reset. This did not help, and after resetting the EMAC I can no longer read PHY registers over MDIO.

When I load Linux instead of our OS, I can see that the reset using the SWR bit works correctly, but I can’t find what is missing in my implementation.

Any help would be greatly appreciated.

Thanks,

Sarah

 

For additional context, I read the following values before putting the EMAC2 in reset:

PHY ID1: 0x283

Main PLLGLOB: 35000103

Per PLLGLOB: 35000103

DMA_Mode: 00000001

SYSMGR_TSN2: 1

EMAC2_DWCXG_CORE_MAC_TX_CONF: 0

CLKMGR_PERPLL_EN: fffffff

CLKMGR_PERPLL_BYPASS: 0

CLKMGR_PERPLL_EMACCTL: 0

CLKMGR_CTLGRP_EMACACTR: 10001

CLKMGR_CTLGRP_EMACPTPCTR: 0

CLKMGR_CTLGRP_EXTCNTRST: 0

Hps Debug
Sw Development

7 Replies

  • SarahTr's avatar
    SarahTr
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    5 months ago

    Hello Kian,
    Thank you for your reply.
    The issue turned out to be missing IO control register configurations.
    Our adaptations in the U-Boot to load INOS overwrote IO control register writes done in the boot command for the AXE5-Eagle board.
    After adding them back in, the software reset worked.
    Thanks,
    Sarah

    • KianHinT_altera's avatar
      KianHinT_altera
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      5 months ago

      Hi SarahTr​ 

      Thanks for sharing out your solution to this issue. With that in mind , I will transition this thread to community support for future reference.

      Thanks

      Regards

      Kian

  • KianHinT_altera's avatar
    KianHinT_altera
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    5 months ago

    Hi SarahTr​ 

    Sorry for the long delay as I didnt notice your reply after coming back from festive holiday . May I know the status for this case, whether have you resolved it?

    I do not personally used INOS before so I couldnt advice much on that end. Anyway if you still having trouble, you could try dumping the registers out on the working linux , and compare with the INOS registers,

    eg. 

    Boot Linux on the Agilex5 board that you have. Then using devmem to read/dump out the register Clock Manager, Reset Manager and System Manager then compare with INOS just before you set bit 1 to SWR, see any differences there

    Probably can focus on the Clock Manager first see any differences

    eg,
    CLKMGR_PERPLL_EN: fffffff

    CLKMGR_PERPLL_EMACCTL: 0

    In Agilex5 HPS register map , these translate into 

    https://www.intel.com/content/www/us/en/programmable/hps/agilex5/topics/index.html#register_perpllgrp_en.html

    https://www.intel.com/content/www/us/en/programmable/hps/agilex5/topics/index.html#register_perpllgrp_emacctl.html

    Thanks

    Regards

    Kian

  • SarahTr's avatar
    SarahTr
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    6 months ago

    Hello Erica and Kian,

    Thank you for your suggestions.

    I’m writing the driver for our custom OS called INOS. It's structured differently than Linux, so unfortunately I can’t directly compare device trees.

    The EMAC should be enabled: the tsn2 and tsn2ecc bits in the Reset_Mgr.per0modrst register are cleared.

    I compared the clock manager configuration with what I found in the HPS Technical Reference Manual, but I haven’t been able to fully confirm that the clock setup is correct. Is there a recommended way to verify that the clocks are configured and connected as expected?

  • KianHinT_altera's avatar
    KianHinT_altera
    Icon for Frequent Contributor rankFrequent Contributor
    6 months ago

    Thanks Erica for the advice on this issue.

     

    Hi Sarah,

    Since you mention that Linux is working and the OS that you're using is not, as Erica mentioned, I would suspect the device tree is not set properly for your OS, could you check on this first to see whether it is configured correctly, probably you can compare with the Linux since that is working.

     

    Thanks

    Regards

    Kian

  • ErikaP_Arrow's avatar
    ErikaP_Arrow
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    6 months ago

    Hello Sarah, 

    In this case, there is a difference between Linux and your OS.    More precisely, you mentioned that when you use Linux, the reset worked correctly.  However, you see this issue in your OS.

    As such, are you able to state what OS that you are using?

    Since there are some changes between the Linux and your OS, have you checked the device tree (.dtsi) file?  In particular,  have you double-checked the EMAC section?     Is the emac disabled/enabled (it should be enabled) and is the clock connection correct?