Forum Discussion
Occasional ContributorXcelium support for Agilex P-tile PCIe simulations
Hi Wincent,
Apologies for the delay in responding to your prior follow-up email.
Yes, you can close this ticket.
Thank you for the support.
Regards
Binu
Occasional ContributorHi Wincent,
OK. I am getting clarity on the backward compatibility. There are two things I see:
- enabling the Header checkbox from R-tile IP GUI gives a P-tile style (big endian) header
- The pins are not exactly backward compatible as per the above link as the R-tile ports have "st" marking
Going back to my Question 1:
- Can you check and confirm if there are any fundamental functionality differences between a P-tile and R-tile IP?
- Say for example, if I generate a R-tile IP in Gen3,2x8 mode with TLP header enabled in GUI and this works in simulation, can I replace it with a P-tile Gen3, 2x8 mode IP later if needed and expect same functionality?
Can you confirm despite the minor pin name differences, whether functionality of P-tile vs R-tile for a particular Gen of PCIe remains the same?
Thanks
Binu
Regular ContributorHi,
For your question 1, for sure there is some difference between P-tile and R-tile IP.
For example some of the pin assignment, pin name, and some adding features such as PIPE direct mode.
I do not recommend you to simply generate any design and replace it with P-tile.
But theoretically, you can do it, but we never test it on our place before.
for the fundamental different, you can refer to
https://www.intel.com/content/www/us/en/products/details/fpga/intellectual-property/interface-protocols/pcie-p-tile-hard-ip.html
Regards,
Wincent_Intel
